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| author | Rex Zhu <Rex.Zhu@amd.com> | 2015-11-19 05:47:36 (GMT) |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2015-12-21 21:42:40 (GMT) |
| commit | aceae1bfd91d73965a165b72f55678e5f6337448 (patch) | |
| tree | 9ed171969b05435e0fe0ef17098338aecb6a4d93 | |
| parent | 73c9f222889986d6f0ba0708115337a0284a5b61 (diff) | |
| download | linux-aceae1bfd91d73965a165b72f55678e5f6337448.tar.xz | |
drm/amd/powerplay: add smc msg for NB P-State switch
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/cz_ppsmc.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h | 8 |
2 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/inc/cz_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/cz_ppsmc.h index 273616a..9b69878 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/cz_ppsmc.h +++ b/drivers/gpu/drm/amd/powerplay/inc/cz_ppsmc.h @@ -164,6 +164,7 @@ enum DPM_ARRAY { #define PPSMC_MSG_SetLoggerAddressHigh ((uint16_t) 0x26C) #define PPSMC_MSG_SetLoggerAddressLow ((uint16_t) 0x26D) #define PPSMC_MSG_SetWatermarkFrequency ((uint16_t) 0x26E) +#define PPSMC_MSG_SetDisplaySizePowerParams ((uint16_t) 0x26F) /* REMOVE LATER*/ #define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104) diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h b/drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h index 5c9cc3c..0c37c94 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h @@ -48,6 +48,14 @@ struct SMU8_Port80MonitorTable { uint8_t EnableDramShadow; }; +/* Display specific power management parameters */ +#define PWRMGT_SEPARATION_TIME_SHIFT 0 +#define PWRMGT_SEPARATION_TIME_MASK 0xFFFF +#define PWRMGT_DISABLE_CPU_CSTATES_SHIFT 16 +#define PWRMGT_DISABLE_CPU_CSTATES_MASK 0x1 +#define PWRMGT_DISABLE_CPU_PSTATES_SHIFT 24 +#define PWRMGT_DISABLE_CPU_PSTATES_MASK 0x1 + /* Clock Table Definitions */ #define NUM_SCLK_LEVELS 8 #define NUM_LCLK_LEVELS 8 |