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author | Yuantian Tang <andy.tang@nxp.com> | 2017-12-04 07:59:29 (GMT) |
---|---|---|
committer | Xie Xiaobo <xiaobo.xie@nxp.com> | 2017-12-12 09:37:56 (GMT) |
commit | b62b10a57ae9fe6dcb5bf392b05142e37e697e31 (patch) | |
tree | 639216ebe87aed2d9006a01f687b84f16547a95a | |
parent | a5e5a7bcf3bae018e65f090dec0062c2cbf36de8 (diff) | |
download | linux-b62b10a57ae9fe6dcb5bf392b05142e37e697e31.tar.xz |
clk: qoriq: add more divider clocks support
More divider clocks are needed for IP use. So enlarge the PLL divider
array to accommodate more divider clocks.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
-rw-r--r-- | Documentation/devicetree/bindings/clock/qoriq-clock.txt | 1 | ||||
-rw-r--r-- | drivers/clk/clk-qoriq.c | 9 |
2 files changed, 9 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index 1bd2c76..737148e 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -69,6 +69,7 @@ second cell is the clock index for the specified type. 2 hwaccel index (n in CLKCGnHWACSR) 3 fman 0 for fm1, 1 for fm2 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4 + 4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8 3. Example diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index 0e7de00..d62ccb2 100644 --- a/drivers/clk/clk-qoriq.c +++ b/drivers/clk/clk-qoriq.c @@ -41,7 +41,7 @@ struct clockgen_pll_div { }; struct clockgen_pll { - struct clockgen_pll_div div[4]; + struct clockgen_pll_div div[8]; }; #define CLKSEL_VALID 1 @@ -1127,6 +1127,13 @@ static void __init create_one_pll(struct clockgen *cg, int idx) struct clk *clk; int ret; + /* + * For platform PLL, there are 8 divider clocks. + * For core PLL, there are 4 divider clocks at most. + */ + if (idx != 0 && i >= 4) + break; + snprintf(pll->div[i].name, sizeof(pll->div[i].name), "cg-pll%d-div%d", idx, i + 1); |