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author | Olof Johansson <olof@lixom.net> | 2014-05-31 03:32:48 (GMT) |
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committer | Olof Johansson <olof@lixom.net> | 2014-05-31 03:32:48 (GMT) |
commit | bb195016513513c78954678c22d30a4b2d4a6b1f (patch) | |
tree | 1d315ac59099d7b0700b3050f2dab2bdd0b1f050 | |
parent | e1134cb6b3b8baa6d5d8dc858b9e71f7a060db4f (diff) | |
parent | f46d23f6f3676720de2a3f195413a5e69f202238 (diff) | |
download | linux-bb195016513513c78954678c22d30a4b2d4a6b1f.tar.xz |
Merge tag 'qcom-dt-for-3.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/dt
Merge "Qualcomm ARM Based Device Tree Updates for v3.16-2" from Kumar Gala:
* Updated MSM8660/MSM8960/MSM8974 dts for various updates or conformitity
to binding specs
* Added APQ8064 SoC and IFC6410 board device tree support
* Added APQ8084 SoC and APQ8084-MTP board device tree support
* tag 'qcom-dt-for-3.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom:
ARM: dts: qcom: Add APQ8084-MTP board support
ARM: dts: qcom: Add APQ8084 SoC support
ARM: dts: qcom: Add initial APQ8064 SoC and IFC6410 board device trees
ARM: dts: qcom: Update msm8660 device trees
ARM: dts: qcom: Update msm8960 device trees
ARM: dts: qcom: Update msm8974/apq8074 device trees
Signed-off-by: Olof Johansson <olof@lixom.net>
-rw-r--r-- | arch/arm/boot/dts/Makefile | 9 | ||||
-rw-r--r-- | arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 16 | ||||
-rw-r--r-- | arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi | 1 | ||||
-rw-r--r-- | arch/arm/boot/dts/qcom-apq8064.dtsi | 170 | ||||
-rw-r--r-- | arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 28 | ||||
-rw-r--r-- | arch/arm/boot/dts/qcom-apq8084-mtp.dts | 6 | ||||
-rw-r--r-- | arch/arm/boot/dts/qcom-apq8084.dtsi | 179 | ||||
-rw-r--r-- | arch/arm/boot/dts/qcom-msm8660-surf.dts | 10 | ||||
-rw-r--r-- | arch/arm/boot/dts/qcom-msm8660.dtsi | 115 | ||||
-rw-r--r-- | arch/arm/boot/dts/qcom-msm8960-cdp.dts | 10 | ||||
-rw-r--r-- | arch/arm/boot/dts/qcom-msm8960.dtsi | 176 | ||||
-rw-r--r-- | arch/arm/boot/dts/qcom-msm8974.dtsi | 49 | ||||
-rw-r--r-- | arch/arm/mach-qcom/board.c | 4 |
13 files changed, 612 insertions, 161 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b350409..33409a3 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -308,9 +308,12 @@ dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \ orion5x-maxtor-shared-storage-2.dtb \ orion5x-rd88f5182-nas.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb -dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \ - qcom-msm8960-cdp.dtb \ - qcom-apq8074-dragonboard.dtb +dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8064-ifc6410.dtb \ + qcom-apq8074-dragonboard.dtb \ + qcom-apq8084-mtp.dtb \ + qcom-msm8660-surf.dtb \ + qcom-msm8960-cdp.dtb dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ s3c6410-smdk6410.dtb diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts new file mode 100644 index 0000000..7c2441d --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -0,0 +1,16 @@ +#include "qcom-apq8064-v2.0.dtsi" + +/ { + model = "Qualcomm APQ8064/IFC6410"; + compatible = "qcom,apq8064-ifc6410", "qcom,apq8064"; + + soc { + gsbi@16600000 { + status = "ok"; + qcom,mode = <GSBI_PROT_I2C_UART>; + serial@16640000 { + status = "ok"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi new file mode 100644 index 0000000..935c394 --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi @@ -0,0 +1 @@ +#include "qcom-apq8064.dtsi" diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi new file mode 100644 index 0000000..92bf793 --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -0,0 +1,170 @@ +/dts-v1/; + +#include "skeleton.dtsi" +#include <dt-bindings/clock/qcom,gcc-msm8960.h> +#include <dt-bindings/soc/qcom,gsbi.h> + +/ { + model = "Qualcomm APQ8064"; + compatible = "qcom,apq8064"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + }; + + cpu@1 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + }; + + cpu@2 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + qcom,acc = <&acc2>; + qcom,saw = <&saw2>; + }; + + cpu@3 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + qcom,acc = <&acc3>; + qcom,saw = <&saw3>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = <1 10 0x304>; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; + }; + + timer@200a000 { + compatible = "qcom,kpss-timer", "qcom,msm-timer"; + interrupts = <1 1 0x301>, + <1 2 0x301>, + <1 3 0x301>; + reg = <0x0200a000 0x100>; + clock-frequency = <27000000>, + <32768>; + cpu-offset = <0x80000>; + }; + + acc0: clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + }; + + acc1: clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + }; + + acc2: clock-controller@20a8000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; + }; + + acc3: clock-controller@20b8000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; + }; + + saw0: regulator@2089000 { + compatible = "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + saw1: regulator@2099000 { + compatible = "qcom,saw2"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + saw2: regulator@20a9000 { + compatible = "qcom,saw2"; + reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + saw3: regulator@20b9000 { + compatible = "qcom,saw2"; + reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + gsbi7: gsbi@16600000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16600000 0x100>; + clocks = <&gcc GSBI7_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + serial@16640000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16640000 0x1000>, + <0x16600000 0x1000>; + interrupts = <0 158 0x0>; + clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x00500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-apq8064"; + reg = <0x00900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index 92320c4..b4dfb01 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -4,7 +4,11 @@ model = "Qualcomm APQ8074 Dragonboard"; compatible = "qcom,apq8074-dragonboard", "qcom,apq8074"; - soc: soc { + soc { + serial@f991e000 { + status = "ok"; + }; + sdhci@f9824900 { bus-width = <8>; non-removable; @@ -15,5 +19,27 @@ cd-gpios = <&msmgpio 62 0x1>; bus-width = <4>; }; + + + pinctrl@fd510000 { + spi8_default: spi8_default { + mosi { + pins = "gpio45"; + function = "blsp_spi8"; + }; + miso { + pins = "gpio46"; + function = "blsp_spi8"; + }; + cs { + pins = "gpio47"; + function = "blsp_spi8"; + }; + clk { + pins = "gpio48"; + function = "blsp_spi8"; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom-apq8084-mtp.dts new file mode 100644 index 0000000..9dae387 --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8084-mtp.dts @@ -0,0 +1,6 @@ +#include "qcom-apq8084.dtsi" + +/ { + model = "Qualcomm APQ 8084-MTP"; + compatible = "qcom,apq8084-mtp", "qcom,apq8084"; +}; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi new file mode 100644 index 0000000..e3e009a --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -0,0 +1,179 @@ +/dts-v1/; + +#include "skeleton.dtsi" + +/ { + model = "Qualcomm APQ 8084"; + compatible = "qcom,apq8084"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <0>; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <1>; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <2>; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; + qcom,acc = <&acc2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <3>; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; + qcom,acc = <&acc3>; + }; + + L2: l2-cache { + compatible = "qcom,arch-cache"; + cache-level = <2>; + qcom,saw = <&saw_l2>; + }; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = <1 7 0xf04>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0xf08>, + <1 3 0xf08>, + <1 4 0xf08>, + <1 1 0xf08>; + clock-frequency = <19200000>; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + clock-frequency = <19200000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + saw_l2: regulator@f9012000 { + compatible = "qcom,saw2"; + reg = <0xf9012000 0x1000>; + regulator; + }; + + acc0: clock-controller@f9088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9088000 0x1000>, + <0xf9008000 0x1000>; + }; + + acc1: clock-controller@f9098000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9098000 0x1000>, + <0xf9008000 0x1000>; + }; + + acc2: clock-controller@f90a8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf90a8000 0x1000>, + <0xf9008000 0x1000>; + }; + + acc3: clock-controller@f90b8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf90b8000 0x1000>, + <0xf9008000 0x1000>; + }; + + restart@fc4ab000 { + compatible = "qcom,pshold"; + reg = <0xfc4ab000 0x4>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts index 169bad9..45180ad 100644 --- a/arch/arm/boot/dts/qcom-msm8660-surf.dts +++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts @@ -3,4 +3,14 @@ / { model = "Qualcomm MSM8660 SURF"; compatible = "qcom,msm8660-surf", "qcom,msm8660"; + + soc { + gsbi@19c00000 { + status = "ok"; + qcom,mode = <GSBI_PROT_I2C_UART>; + serial@19c40000 { + status = "ok"; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index c52a9e9..53837aaa2f 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -3,6 +3,7 @@ /include/ "skeleton.dtsi" #include <dt-bindings/clock/qcom,gcc-msm8660.h> +#include <dt-bindings/soc/qcom,gsbi.h> / { model = "Qualcomm MSM8660"; @@ -12,16 +13,18 @@ cpus { #address-cells = <1>; #size-cells = <0>; - compatible = "qcom,scorpion"; - enable-method = "qcom,gcc-msm8660"; cpu@0 { + compatible = "qcom,scorpion"; + enable-method = "qcom,gcc-msm8660"; device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; }; cpu@1 { + compatible = "qcom,scorpion"; + enable-method = "qcom,gcc-msm8660"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; @@ -33,55 +36,73 @@ }; }; - intc: interrupt-controller@2080000 { - compatible = "qcom,msm-8660-qgic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = < 0x02080000 0x1000 >, - < 0x02081000 0x1000 >; - }; + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; - timer@2000000 { - compatible = "qcom,scss-timer", "qcom,msm-timer"; - interrupts = <1 0 0x301>, - <1 1 0x301>, - <1 2 0x301>; - reg = <0x02000000 0x100>; - clock-frequency = <27000000>, - <32768>; - cpu-offset = <0x40000>; - }; + intc: interrupt-controller@2080000 { + compatible = "qcom,msm-8660-qgic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x02080000 0x1000 >, + < 0x02081000 0x1000 >; + }; - msmgpio: gpio@800000 { - compatible = "qcom,msm-gpio"; - reg = <0x00800000 0x4000>; - gpio-controller; - #gpio-cells = <2>; - ngpio = <173>; - interrupts = <0 16 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - }; + timer@2000000 { + compatible = "qcom,scss-timer", "qcom,msm-timer"; + interrupts = <1 0 0x301>, + <1 1 0x301>, + <1 2 0x301>; + reg = <0x02000000 0x100>; + clock-frequency = <27000000>, + <32768>; + cpu-offset = <0x40000>; + }; - gcc: clock-controller@900000 { - compatible = "qcom,gcc-msm8660"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0x900000 0x4000>; - }; + msmgpio: gpio@800000 { + compatible = "qcom,msm-gpio"; + reg = <0x00800000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + ngpio = <173>; + interrupts = <0 16 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + }; - serial@19c40000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x19c40000 0x1000>, - <0x19c00000 0x1000>; - interrupts = <0 195 0x0>; - clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; - clock-names = "core", "iface"; - }; + gcc: clock-controller@900000 { + compatible = "qcom,gcc-msm8660"; + #clock-cells = <1>; + #reset-cells = <1>; + reg = <0x900000 0x4000>; + }; + + gsbi12: gsbi@19c00000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x19c00000 0x100>; + clocks = <&gcc GSBI12_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; + serial@19c40000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x19c40000 0x1000>, + <0x19c00000 0x1000>; + interrupts = <0 195 0x0>; + clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts index a58fb88..8f75cc4 100644 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts @@ -3,4 +3,14 @@ / { model = "Qualcomm MSM8960 CDP"; compatible = "qcom,msm8960-cdp", "qcom,msm8960"; + + soc { + gsbi@16400000 { + status = "ok"; + qcom,mode = <GSBI_PROT_I2C_UART>; + serial@16440000 { + status = "ok"; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 997b7b9..5303e53 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -3,6 +3,7 @@ /include/ "skeleton.dtsi" #include <dt-bindings/clock/qcom,gcc-msm8960.h> +#include <dt-bindings/soc/qcom,gsbi.h> / { model = "Qualcomm MSM8960"; @@ -13,10 +14,10 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <1 14 0x304>; - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; cpu@0 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; @@ -25,6 +26,8 @@ }; cpu@1 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; @@ -35,7 +38,6 @@ L2: l2-cache { compatible = "cache"; cache-level = <2>; - interrupts = <0 2 0x4>; }; }; @@ -45,91 +47,109 @@ qcom,no-pc-write; }; - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = < 0x02000000 0x1000 >, - < 0x02002000 0x1000 >; - }; + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; + }; - timer@200a000 { - compatible = "qcom,kpss-timer", "qcom,msm-timer"; - interrupts = <1 1 0x301>, - <1 2 0x301>, - <1 3 0x301>; - reg = <0x0200a000 0x100>; - clock-frequency = <27000000>, - <32768>; - cpu-offset = <0x80000>; - }; + timer@200a000 { + compatible = "qcom,kpss-timer", "qcom,msm-timer"; + interrupts = <1 1 0x301>, + <1 2 0x301>, + <1 3 0x301>; + reg = <0x0200a000 0x100>; + clock-frequency = <27000000>, + <32768>; + cpu-offset = <0x80000>; + }; - msmgpio: gpio@800000 { - compatible = "qcom,msm-gpio"; - gpio-controller; - #gpio-cells = <2>; - ngpio = <150>; - interrupts = <0 16 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x800000 0x4000>; - }; + msmgpio: gpio@800000 { + compatible = "qcom,msm-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpio = <150>; + interrupts = <0 16 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x800000 0x4000>; + }; - gcc: clock-controller@900000 { - compatible = "qcom,gcc-msm8960"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0x900000 0x4000>; - }; + gcc: clock-controller@900000 { + compatible = "qcom,gcc-msm8960"; + #clock-cells = <1>; + #reset-cells = <1>; + reg = <0x900000 0x4000>; + }; - clock-controller@4000000 { - compatible = "qcom,mmcc-msm8960"; - reg = <0x4000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; + clock-controller@4000000 { + compatible = "qcom,mmcc-msm8960"; + reg = <0x4000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; - }; + acc0: clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + }; - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; - }; + acc1: clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + }; - saw0: regulator@2089000 { - compatible = "qcom,saw2"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; - }; + saw0: regulator@2089000 { + compatible = "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + regulator; + }; - saw1: regulator@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; + saw1: regulator@2099000 { + compatible = "qcom,saw2"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; + }; - serial@16440000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16440000 0x1000>, - <0x16400000 0x1000>; - interrupts = <0 154 0x0>; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - }; + gsbi5: gsbi@16400000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16400000 0x100>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + serial@16440000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16440000 0x1000>, + <0x16400000 0x1000>; + interrupts = <0 154 0x0>; + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - }; + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + }; - rng@1a500000 { - compatible = "qcom,prng"; - reg = <0x1a500000 0x200>; - clocks = <&gcc PRNG_CLK>; - clock-names = "core"; + rng@1a500000 { + compatible = "qcom,prng"; + reg = <0x1a500000 0x200>; + clocks = <&gcc PRNG_CLK>; + clock-names = "core"; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index c530a33..69dca2a 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -13,10 +13,10 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <1 9 0xf04>; - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v2"; cpu@0 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; @@ -24,6 +24,8 @@ }; cpu@1 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; @@ -31,6 +33,8 @@ }; cpu@2 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <2>; next-level-cache = <&L2>; @@ -38,6 +42,8 @@ }; cpu@3 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <3>; next-level-cache = <&L2>; @@ -47,7 +53,6 @@ L2: l2-cache { compatible = "cache"; cache-level = <2>; - interrupts = <0 2 0x4>; qcom,saw = <&saw_l2>; }; }; @@ -57,6 +62,15 @@ interrupts = <1 7 0xf04>; }; + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0xf08>, + <1 3 0xf08>, + <1 4 0xf08>, + <1 1 0xf08>; + clock-frequency = <19200000>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -71,15 +85,6 @@ <0xf9002000 0x1000>; }; - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 2 0xf08>, - <1 3 0xf08>, - <1 4 0xf08>, - <1 1 0xf08>; - clock-frequency = <19200000>; - }; - timer@f9020000 { #address-cells = <1>; #size-cells = <1>; @@ -190,6 +195,7 @@ interrupts = <0 108 0x0>; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + status = "disabled"; }; sdhci@f9824900 { @@ -229,25 +235,6 @@ interrupt-controller; #interrupt-cells = <2>; interrupts = <0 208 0>; - - spi8_default: spi8_default { - mosi { - pins = "gpio45"; - function = "blsp_spi8"; - }; - miso { - pins = "gpio46"; - function = "blsp_spi8"; - }; - cs { - pins = "gpio47"; - function = "blsp_spi8"; - }; - clk { - pins = "gpio48"; - function = "blsp_spi8"; - }; - }; }; }; }; diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c index bae617e..c437a99 100644 --- a/arch/arm/mach-qcom/board.c +++ b/arch/arm/mach-qcom/board.c @@ -15,9 +15,11 @@ #include <asm/mach/arch.h> static const char * const qcom_dt_match[] __initconst = { + "qcom,apq8064", + "qcom,apq8074-dragonboard", + "qcom,apq8084", "qcom,msm8660-surf", "qcom,msm8960-cdp", - "qcom,apq8074-dragonboard", NULL }; |