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authorEzequiel Garcia <ezequiel.garcia@free-electrons.com>2013-08-12 17:14:48 (GMT)
committerDavid Woodhouse <David.Woodhouse@intel.com>2013-08-30 20:34:51 (GMT)
commitcd9d11820f4232856d6254a29fbb9c4f51a981c2 (patch)
tree905bc413c07bc79bf0b6d72b974ee81c03e5d34a
parentc0f3b8643a6fa2461d70760ec49d21d2b031d611 (diff)
downloadlinux-cd9d11820f4232856d6254a29fbb9c4f51a981c2.tar.xz
mtd: nand: pxa3xx: Handle ECC and DMA enable/disable properly
When ECC is not selected, the ECC enable bit must be cleared in the NAND control register. Same applies to DMA. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Daniel Mack <zonque@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
-rw-r--r--drivers/mtd/nand/pxa3xx_nand.c13
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index c4bff66..1dcda6b 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -314,8 +314,17 @@ static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
uint32_t ndcr;
ndcr = host->reg_ndcr;
- ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
- ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
+
+ if (info->use_ecc)
+ ndcr |= NDCR_ECC_EN;
+ else
+ ndcr &= ~NDCR_ECC_EN;
+
+ if (info->use_dma)
+ ndcr |= NDCR_DMA_EN;
+ else
+ ndcr &= ~NDCR_DMA_EN;
+
ndcr |= NDCR_ND_RUN;
/* clear status bits and run */