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author | David Daney <david.daney@cavium.com> | 2011-08-30 13:45:20 (GMT) |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2011-09-21 15:54:02 (GMT) |
commit | d968275921f9fa7fbc602ac6618ffec6a062ee3c (patch) | |
tree | 3bb871afdf4adcc13d006cbe549b454afe242741 | |
parent | 465aaed0030b23d905f3eca5e65481773bea9ea1 (diff) | |
download | linux-d968275921f9fa7fbc602ac6618ffec6a062ee3c.tar.xz |
MIPS: Don't clobber CP0_STATUS value for CONFIG_MIPS_MT_SMTC
Reported-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/2753/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r-- | arch/mips/include/asm/stackframe.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index b4ba244..cb41af5 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -195,9 +195,9 @@ * to cover the pipeline delay. */ .set mips32 - mfc0 v1, CP0_TCSTATUS + mfc0 k0, CP0_TCSTATUS .set mips0 - LONG_S v1, PT_TCSTATUS(sp) + LONG_S k0, PT_TCSTATUS(sp) #endif /* CONFIG_MIPS_MT_SMTC */ LONG_S $4, PT_R4(sp) LONG_S $5, PT_R5(sp) |