diff options
| author | Emilio López <emilio@elopez.com.ar> | 2013-12-23 03:32:35 (GMT) |
|---|---|---|
| committer | Emilio López <emilio@elopez.com.ar> | 2013-12-28 20:28:23 (GMT) |
| commit | ec5589f7a33956ea3671d198ff170dc51ff2145d (patch) | |
| tree | 4031df901b9dc065272b9b5a0eb7f9d29cccc21e | |
| parent | 6ce4eac1f600b34f2f7f58f9cd8f0503d79e42ae (diff) | |
| download | linux-ec5589f7a33956ea3671d198ff170dc51ff2145d.tar.xz | |
ARM: sunxi: add PLL4 support
This commit adds the PLL4 definition to the sun4i, sun5i and sun7i
device trees. PLL4 is compatible with PLL1.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| -rw-r--r-- | arch/arm/boot/dts/sun4i-a10.dtsi | 7 | ||||
| -rw-r--r-- | arch/arm/boot/dts/sun5i-a10s.dtsi | 7 | ||||
| -rw-r--r-- | arch/arm/boot/dts/sun5i-a13.dtsi | 7 | ||||
| -rw-r--r-- | arch/arm/boot/dts/sun7i-a20.dtsi | 7 |
4 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 319cc6b..a6c1cae 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -66,6 +66,13 @@ clocks = <&osc24M>; }; + pll4: pll4@01c20018 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + }; + /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 5247674..c3f4eed 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -63,6 +63,13 @@ clocks = <&osc24M>; }; + pll4: pll4@01c20018 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + }; + /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index ce8ef2a..8c4a9c3 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -67,6 +67,13 @@ clocks = <&osc24M>; }; + pll4: pll4@01c20018 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + }; + /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index e46cfed..e4a5d37 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -62,6 +62,13 @@ clocks = <&osc24M>; }; + pll4: pll4@01c20018 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + }; + /* * This is a dummy clock, to be used as placeholder on * other mux clocks when a specific parent clock is not |