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authorMikko Perttunen <mikko.perttunen@kapsi.fi>2015-09-15 09:55:15 (GMT)
committerThierry Reding <treding@nvidia.com>2015-09-15 10:54:39 (GMT)
commit10d9be6ebe9199feb7680433a24b564a31a8f9b1 (patch)
tree16a3843c12fcd7c9e9dc75ee49dd57dd525fc650
parent6ff33f3902c3b1c5d0db6b1e2c70b6d76fba357f (diff)
downloadlinux-10d9be6ebe9199feb7680433a24b564a31a8f9b1.tar.xz
clk: tegra: Unlock top rates for Tegra124 DFLL clock
The new determine_rate prototype allows for clock rates exceeding 2^31-1 Hz to be used. Switch the DFLL clock to use determine_rate instead of round_rate and unlock the top rates supported by the Tegra124. Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--drivers/clk/tegra/clk-dfll.c15
-rw-r--r--drivers/clk/tegra/cvb.c7
2 files changed, 8 insertions, 14 deletions
diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
index c2ff859..6a75a74 100644
--- a/drivers/clk/tegra/clk-dfll.c
+++ b/drivers/clk/tegra/clk-dfll.c
@@ -1000,24 +1000,25 @@ static unsigned long dfll_clk_recalc_rate(struct clk_hw *hw,
return td->last_unrounded_rate;
}
-static long dfll_clk_round_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long *parent_rate)
+/* Must use determine_rate since it allows for rates exceeding 2^31-1 */
+static int dfll_clk_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *clk_req)
{
struct tegra_dfll *td = clk_hw_to_dfll(hw);
struct dfll_rate_req req;
int ret;
- ret = dfll_calculate_rate_request(td, &req, rate);
+ ret = dfll_calculate_rate_request(td, &req, clk_req->rate);
if (ret)
return ret;
/*
- * Don't return the rounded rate, since it doesn't really matter as
+ * Don't set the rounded rate, since it doesn't really matter as
* the output rate will be voltage controlled anyway, and cpufreq
* freaks out if any rounding happens.
*/
- return rate;
+
+ return 0;
}
static int dfll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -1033,7 +1034,7 @@ static const struct clk_ops dfll_clk_ops = {
.enable = dfll_clk_enable,
.disable = dfll_clk_disable,
.recalc_rate = dfll_clk_recalc_rate,
- .round_rate = dfll_clk_round_rate,
+ .determine_rate = dfll_clk_determine_rate,
.set_rate = dfll_clk_set_rate,
};
diff --git a/drivers/clk/tegra/cvb.c b/drivers/clk/tegra/cvb.c
index 0204e08..69c74ee 100644
--- a/drivers/clk/tegra/cvb.c
+++ b/drivers/clk/tegra/cvb.c
@@ -78,13 +78,6 @@ static int build_opp_table(const struct cvb_table *d,
if (!table->freq || (table->freq > max_freq))
break;
- /*
- * FIXME after clk_round_rate/clk_determine_rate prototypes
- * have been updated
- */
- if (table->freq & (1<<31))
- continue;
-
dfll_mv = get_cvb_voltage(
speedo_value, d->speedo_scale, &table->coefficients);
dfll_mv = round_cvb_voltage(dfll_mv, d->voltage_scale, align);