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author | Shawn Guo <shawn.guo@linaro.org> | 2013-07-18 05:08:20 (GMT) |
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committer | Shawn Guo <shawn.guo@linaro.org> | 2013-08-22 15:20:37 (GMT) |
commit | 1fa5007b3a71ebf8e9ebc9fd039da5339bd8c3f8 (patch) | |
tree | 446f13cd6c572af1a294f54a361657244020d3a8 | |
parent | 0a036388529477bcce01226a8ba901ef16333393 (diff) | |
download | linux-1fa5007b3a71ebf8e9ebc9fd039da5339bd8c3f8.tar.xz |
ARM: imx6q: add spdif gate clock
It adds the missing spdif gate clock into imx6q clock driver.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-rw-r--r-- | Documentation/devicetree/bindings/clock/imx6q-clock.txt | 1 | ||||
-rw-r--r-- | arch/arm/mach-imx/clk-imx6q.c | 4 |
2 files changed, 4 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt index a0e104f..794d089 100644 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt @@ -209,6 +209,7 @@ clocks and IDs. pll5_post_div 194 pll5_video_div 195 eim_slow 196 + spdif 197 Examples: diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index db9f8f5..d739df1 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -239,7 +239,8 @@ enum mx6q_clks { pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, - usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, clk_max + usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, + spdif, clk_max }; static struct clk *clk[clk_max]; @@ -521,6 +522,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4); clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); + clk[spdif] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14); clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18); clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20); clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22); |