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| author | Michel Dänzer <michel.daenzer@amd.com> | 2014-07-29 09:47:21 (GMT) |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2014-08-05 12:53:41 (GMT) |
| commit | 810b73d1909298b67db5c7c047ed99b487ff7341 (patch) | |
| tree | 8f731bfe4833727d2f7b3232ef3c20461418beaa | |
| parent | 1490434f0da63afc6006411c8829c6a7935a4e7e (diff) | |
| download | linux-810b73d1909298b67db5c7c047ed99b487ff7341.tar.xz | |
drm/radeon: Use write-combined CPU mappings of IBs on >= CIK
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_ring.c | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c index 7cfea7e..20b0e4f 100644 --- a/drivers/gpu/drm/radeon/radeon_ring.c +++ b/drivers/gpu/drm/radeon/radeon_ring.c @@ -201,10 +201,22 @@ int radeon_ib_pool_init(struct radeon_device *rdev) if (rdev->ib_pool_ready) { return 0; } - r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, - RADEON_IB_POOL_SIZE*64*1024, - RADEON_GPU_PAGE_SIZE, - RADEON_GEM_DOMAIN_GTT, 0); + + if (rdev->family >= CHIP_BONAIRE) { + r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, + RADEON_IB_POOL_SIZE*64*1024, + RADEON_GPU_PAGE_SIZE, + RADEON_GEM_DOMAIN_GTT, + RADEON_GEM_GTT_WC); + } else { + /* Before CIK, it's better to stick to cacheable GTT due + * to the command stream checking + */ + r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, + RADEON_IB_POOL_SIZE*64*1024, + RADEON_GPU_PAGE_SIZE, + RADEON_GEM_DOMAIN_GTT, 0); + } if (r) { return r; } |