diff options
| author | Maciej W. Rozycki <macro@linux-mips.org> | 2014-09-25 10:06:45 (GMT) |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2014-09-28 21:22:09 (GMT) |
| commit | b1a6d3ecf806457d3e76ac0044db424be3c9422d (patch) | |
| tree | d0951a96258a0fd38b88f01bf56cbbb525fb0f4f | |
| parent | 8a189f1288b654e45f2ec9393abfb1390b261ae9 (diff) | |
| download | linux-b1a6d3ecf806457d3e76ac0044db424be3c9422d.tar.xz | |
defxx: DEFEA's Burst Holdoff register initialization fix
Use the mask rather than bit number macro to initialize the chip select
control bit for PDQ register space decoding in the Burst Holdoff register.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/fddi/defxx.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/fddi/defxx.c b/drivers/net/fddi/defxx.c index 6068db87..15a18fb 100644 --- a/drivers/net/fddi/defxx.c +++ b/drivers/net/fddi/defxx.c @@ -748,9 +748,9 @@ static void dfx_bus_init(struct net_device *dev) */ val = inb(base_addr + PI_DEFEA_K_BURST_HOLDOFF); if (dfx_use_mmio) - val |= PI_BURST_HOLDOFF_V_MEM_MAP; + val |= PI_BURST_HOLDOFF_M_MEM_MAP; else - val &= ~PI_BURST_HOLDOFF_V_MEM_MAP; + val &= ~PI_BURST_HOLDOFF_M_MEM_MAP; outb(val, base_addr + PI_DEFEA_K_BURST_HOLDOFF); /* Enable interrupts at EISA bus interface chip (ESIC) */ |