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author | Antonio Ospite <ao2@ao2.it> | 2014-06-04 12:03:46 (GMT) |
---|---|---|
committer | Jiri Kosina <jkosina@suse.cz> | 2014-06-19 13:23:36 (GMT) |
commit | b39fc89034b465bdfab13d62b37f1fe49c7577bf (patch) | |
tree | 0129400366ff740e94d3c91791b7de9e4baefe7e | |
parent | 2fba5376ed7d8cdebd873ee124b8e5dd3c936f92 (diff) | |
download | linux-b39fc89034b465bdfab13d62b37f1fe49c7577bf.tar.xz |
mfd: fix comment
Signed-off-by: Antonio Ospite <ao2@ao2.it>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
-rw-r--r-- | drivers/mfd/intel_msic.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mfd/intel_msic.c b/drivers/mfd/intel_msic.c index 049fd23..443e7cd 100644 --- a/drivers/mfd/intel_msic.c +++ b/drivers/mfd/intel_msic.c @@ -27,7 +27,7 @@ /* * MSIC interrupt tree is readable from SRAM at INTEL_MSIC_IRQ_PHYS_BASE. - * Since IRQ block starts from address 0x002 we need to substract that from + * Since IRQ block starts from address 0x002 we need to subtract that from * the actual IRQ status register address. */ #define MSIC_IRQ_STATUS(x) (INTEL_MSIC_IRQ_PHYS_BASE + ((x) - 2)) |