diff options
| author | Sudeep Holla <sudeep.holla@arm.com> | 2016-06-02 09:57:06 (GMT) |
|---|---|---|
| committer | Sudeep Holla <sudeep.holla@arm.com> | 2016-06-21 14:17:16 (GMT) |
| commit | bdeaa21affa696279ed9b676d6e4f8ddc6f42a54 (patch) | |
| tree | cfd1668c63c8aa96c036db963aaba71063a3f672 | |
| parent | 3e287cf6ef954947365a4aca6580ea1d6bee3a18 (diff) | |
| download | linux-bdeaa21affa696279ed9b676d6e4f8ddc6f42a54.tar.xz | |
arm64: dts: juno: add SCPI power domains for device power management
This patch adds power domain information to coresight devices using
SCPI power domains.
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| -rw-r--r-- | arch/arm64/boot/dts/arm/juno-base.dtsi | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 4ea40a4..53820fa 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -67,6 +67,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; ports { #address-cells = <1>; #size-cells = <0>; @@ -96,6 +97,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; port { tpiu_in_port: endpoint { slave-mode; @@ -110,6 +112,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; ports { #address-cells = <1>; #size-cells = <0>; @@ -146,6 +149,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; port { etr_in_port: endpoint { slave-mode; @@ -160,6 +164,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; port { cluster0_etm0_out_port: endpoint { remote-endpoint = <&cluster0_funnel_in_port0>; @@ -173,6 +178,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; ports { #address-cells = <1>; #size-cells = <0>; @@ -208,6 +214,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; port { cluster0_etm1_out_port: endpoint { remote-endpoint = <&cluster0_funnel_in_port1>; @@ -221,6 +228,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; port { cluster1_etm0_out_port: endpoint { remote-endpoint = <&cluster1_funnel_in_port0>; @@ -234,6 +242,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; ports { #address-cells = <1>; #size-cells = <0>; @@ -283,6 +292,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; port { cluster1_etm1_out_port: endpoint { remote-endpoint = <&cluster1_funnel_in_port1>; @@ -296,6 +306,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; port { cluster1_etm2_out_port: endpoint { remote-endpoint = <&cluster1_funnel_in_port2>; @@ -309,6 +320,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; port { cluster1_etm3_out_port: endpoint { remote-endpoint = <&cluster1_funnel_in_port3>; @@ -416,6 +428,12 @@ }; }; + scpi_devpd: scpi-power-domains { + compatible = "arm,scpi-power-domains"; + num-domains = <2>; + #power-domain-cells = <1>; + }; + scpi_sensors0: sensors { compatible = "arm,scpi-sensors"; #thermal-sensor-cells = <1>; |