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| author | Dongsheng Wang <dongsheng.wang@freescale.com> | 2013-05-14 08:05:56 (GMT) |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2013-07-30 20:50:08 (GMT) |
| commit | e00c9a0c2ef8aacb2e63121fcce69687c8d932ca (patch) | |
| tree | 9c50f5ff50e3ae980dcb3a4d292b68e2566bc9b5 | |
| parent | f8dc6eb757c3351e282678528d052f7a4c0e44c9 (diff) | |
| download | linux-e00c9a0c2ef8aacb2e63121fcce69687c8d932ca.tar.xz | |
powerpc/mpc85xx: invalidate TLB after hibernation resume
This problem belongs to the core synchronization issues.
The cpu1 already updated spin_table values, but bootcore cannot get
this value in time.
After bootcpu hibiernation restore the pages. we are now running
with the kernel data of the old kernel fully restored. if we reset
the non-bootcpus that will be reset cache(tlb), the non-bootcpus
will get new address(map virtual and physical address spaces).
but bootcpu tlb cache still use boot kernel data, so we need to
invalidate the bootcpu tlb cache make it to get new main memory data.
log:
Enabling non-boot CPUs ...
smp_85xx_kick_cpu: timeout waiting for core 1 to reset
smp: failed starting cpu 1 (rc -2)
Error taking CPU1 up: -2
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: Anton Vorontsov <anton@enomsg.org>
[scottwood@freescale.com: reworded code comment for clarity]
Signed-off-by: Scott Wood <scottwood@freescale.com>
| -rw-r--r-- | arch/powerpc/kernel/swsusp_booke.S | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/swsusp_booke.S b/arch/powerpc/kernel/swsusp_booke.S index 11a3930..0f20405 100644 --- a/arch/powerpc/kernel/swsusp_booke.S +++ b/arch/powerpc/kernel/swsusp_booke.S @@ -141,6 +141,14 @@ _GLOBAL(swsusp_arch_resume) lis r11,swsusp_save_area@h ori r11,r11,swsusp_save_area@l + /* + * Mappings from virtual addresses to physical addresses may be + * different than they were prior to restoring hibernation state. + * Invalidate the TLB so that the boot CPU is using the new + * mappings. + */ + bl _tlbil_all + lwz r4,SL_SPRG0(r11) mtsprg 0,r4 lwz r4,SL_SPRG1(r11) |