diff options
author | Alexandre Belloni <alexandre.belloni@free-electrons.com> | 2014-11-07 20:58:21 (GMT) |
---|---|---|
committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2014-11-13 11:03:44 (GMT) |
commit | f0a0a58e6f46c2dded813ee860b9cbd795b4e571 (patch) | |
tree | e73acda80e9ed29f6597c52195007c362738c6f3 | |
parent | 93d2cf468adfcbb58895cc1d4052099e23392c82 (diff) | |
download | linux-f0a0a58e6f46c2dded813ee860b9cbd795b4e571.tar.xz |
ARM: at91: move sdramc/ddrsdr header to include/soc/at91
Move the (DDR) SDRAM controller headers to include/soc/at91 to remove the
dependency on mach/ headers from the at91-reset driver.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-rw-r--r-- | MAINTAINERS | 1 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_ramc.h | 6 | ||||
-rw-r--r-- | arch/arm/mach-at91/pm.h | 1 | ||||
-rw-r--r-- | drivers/power/reset/at91-reset.c | 4 | ||||
-rw-r--r-- | include/soc/at91/at91rm9200_sdramc.h (renamed from arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h) | 0 | ||||
-rw-r--r-- | include/soc/at91/at91sam9_ddrsdr.h (renamed from arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h) | 0 | ||||
-rw-r--r-- | include/soc/at91/at91sam9_sdramc.h (renamed from arch/arm/mach-at91/include/mach/at91sam9_sdramc.h) | 0 |
7 files changed, 6 insertions, 6 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index dab92a7..9b604e7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -861,6 +861,7 @@ W: http://maxim.org.za/at91_26.html W: http://www.linux4sam.org S: Supported F: arch/arm/mach-at91/ +F: include/soc/at91/ F: arch/arm/boot/dts/at91*.dts F: arch/arm/boot/dts/at91*.dtsi F: arch/arm/boot/dts/sama*.dts diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h index d8aeb27..e4492b1 100644 --- a/arch/arm/mach-at91/include/mach/at91_ramc.h +++ b/arch/arm/mach-at91/include/mach/at91_ramc.h @@ -25,8 +25,8 @@ extern void __iomem *at91_ramc_base[]; #define AT91_MEMCTRL_SDRAMC 1 #define AT91_MEMCTRL_DDRSDR 2 -#include <mach/at91rm9200_sdramc.h> -#include <mach/at91sam9_ddrsdr.h> -#include <mach/at91sam9_sdramc.h> +#include <soc/at91/at91rm9200_sdramc.h> +#include <soc/at91/at91sam9_ddrsdr.h> +#include <soc/at91/at91sam9_sdramc.h> #endif /* __AT91_RAMC_H__ */ diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index c5101dc..d2c8996 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -14,7 +14,6 @@ #include <asm/proc-fns.h> #include <mach/at91_ramc.h> -#include <mach/at91rm9200_sdramc.h> #ifdef CONFIG_PM extern void at91_pm_set_standby(void (*at91_standby)(void)); diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c index 3cb3669..69a75d99 100644 --- a/drivers/power/reset/at91-reset.c +++ b/drivers/power/reset/at91-reset.c @@ -19,8 +19,8 @@ #include <asm/system_misc.h> -#include <mach/at91sam9_ddrsdr.h> -#include <mach/at91sam9_sdramc.h> +#include <soc/at91/at91sam9_ddrsdr.h> +#include <soc/at91/at91sam9_sdramc.h> #define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */ #define AT91_RSTC_PROCRST BIT(0) /* Processor Reset */ diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h b/include/soc/at91/at91rm9200_sdramc.h index aa047f45..aa047f45 100644 --- a/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h +++ b/include/soc/at91/at91rm9200_sdramc.h diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/include/soc/at91/at91sam9_ddrsdr.h index 0210797..0210797 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h +++ b/include/soc/at91/at91sam9_ddrsdr.h diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/include/soc/at91/at91sam9_sdramc.h index 3d085a9..3d085a9 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h +++ b/include/soc/at91/at91sam9_sdramc.h |