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author | Xie Xiaobo <xiaobo.xie@nxp.com> | 2017-12-12 08:12:33 (GMT) |
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committer | Xie Xiaobo <xiaobo.xie@nxp.com> | 2017-12-12 08:12:33 (GMT) |
commit | c0246a9ec4d461ef4dd7647f94005380bb9e7f0b (patch) | |
tree | 7588601aa6ce98f5e9fd083a1b351d9023c0b295 /Documentation/devicetree/bindings/arm/arch_timer.txt | |
parent | 50fd1a6d79d48a7c35890aecce5a5d6b872a461d (diff) | |
parent | 56f4a560c6d6318b5a8e18a1b3e44909a5158d1e (diff) | |
download | linux-c0246a9ec4d461ef4dd7647f94005380bb9e7f0b.tar.xz |
Merge Linaro linux 4.9.62 into linux-4.9
Signed-off-by: Xiaobo Xie <xiaobo.xie@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/arm/arch_timer.txt')
-rw-r--r-- | Documentation/devicetree/bindings/arm/arch_timer.txt | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt index ad440a2..e926aea 100644 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt @@ -31,6 +31,12 @@ to deliver its interrupts via SPIs. This also affects writes to the tval register, due to the implicit counter read. +- hisilicon,erratum-161010101 : A boolean property. Indicates the + presence of Hisilicon erratum 161010101, which says that reading the + counters is unreliable in some cases, and reads may return a value 32 + beyond the correct value. This also affects writes to the tval + registers, due to the implicit counter read. + ** Optional properties: - arm,cpu-registers-not-fw-configured : Firmware does not initialize |