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author | Stephen Boyd <sboyd@codeaurora.org> | 2016-04-15 23:02:46 (GMT) |
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committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-04-15 23:02:46 (GMT) |
commit | 75ff88888093eddca478a8fa1b77b30edb4fa8be (patch) | |
tree | 97990ff554f2e37084fa69a8fee891c13eb287be /Documentation/devicetree/bindings/clock | |
parent | c02b73c943d723511abecde7909d0818638d1bc2 (diff) | |
parent | 33b8ac917a8f7a22fa3d779f875646201d0097a0 (diff) | |
download | linux-75ff88888093eddca478a8fa1b77b30edb4fa8be.tar.xz |
Merge branch 'clk-artpec6' into clk-next
* clk-artpec6:
clk: add artpec-6 clock controller
clk: add device tree binding for Artpec-6 clock controller
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
-rw-r--r-- | Documentation/devicetree/bindings/clock/artpec6.txt | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/artpec6.txt b/Documentation/devicetree/bindings/clock/artpec6.txt new file mode 100644 index 0000000..dff9cdf --- /dev/null +++ b/Documentation/devicetree/bindings/clock/artpec6.txt @@ -0,0 +1,41 @@ +* Clock bindings for Axis ARTPEC-6 chip + +The bindings are based on the clock provider binding in +Documentation/devicetree/bindings/clock/clock-bindings.txt + +External clocks: +---------------- + +There are two external inputs to the main clock controller which should be +provided using the common clock bindings. +- "sys_refclk": External 50 Mhz oscillator (required) +- "i2s_refclk": Alternate audio reference clock (optional). + +Main clock controller +--------------------- + +Required properties: +- #clock-cells: Should be <1> + See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers. +- compatible: Should be "axis,artpec6-clkctrl" +- reg: Must contain the base address and length of the system controller +- clocks: Must contain a phandle entry for each clock in clock-names +- clock-names: Must include the external oscillator ("sys_refclk"). Optional + ones are the audio reference clock ("i2s_refclk") and the audio fractional + dividers ("frac_clk0" and "frac_clk1"). + +Examples: + +ext_clk: ext_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; +}; + +clkctrl: clkctrl@f8000000 { + #clock-cells = <1>; + compatible = "axis,artpec6-clkctrl"; + reg = <0xf8000000 0x48>; + clocks = <&ext_clk>; + clock-names = "sys_refclk"; +}; |