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author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-03-23 16:38:28 (GMT) |
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committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-04-21 22:29:23 (GMT) |
commit | 7f2ea3847d47d49929d41573a3b26c80ddebbef5 (patch) | |
tree | f7a4ab1eadcea14597f1f2ad9bd8cb8bbda6f4a0 /Documentation/devicetree/bindings/clock | |
parent | f4b9ef653c047165f096d32816904be5ee337a63 (diff) | |
download | linux-7f2ea3847d47d49929d41573a3b26c80ddebbef5.tar.xz |
dt-bindings: clk: sun5i: add DRAM gates compatible
The Allwinner SoCs have a gate controller to gate the access to the DRAM
clock to the some devices that need to access the DRAM directly (mostly
display / image related IPs).
Use a simple gates driver to support the one found in the A13 / R8 SoCs.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
-rw-r--r-- | Documentation/devicetree/bindings/clock/sunxi.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 9de34a8..1bf588e 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -64,6 +64,7 @@ Required properties: "allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3 "allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80 "allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10 + "allwinner,sun5i-a13-dram-gates-clk" - for the DRAM gates on A13 "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13 "allwinner,sun4i-a10-mmc-clk" - for the MMC clock "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80 |