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author | Fabio Estevam <fabio.estevam@nxp.com> | 2016-04-01 23:52:16 (GMT) |
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committer | Shawn Guo <shawnguo@kernel.org> | 2016-04-13 09:47:58 (GMT) |
commit | 3883dd74f0101d3ec94b213456c5965467ac8da9 (patch) | |
tree | b6defae402398809189229ff7b38a1f6c39e7af9 /Documentation/devicetree/bindings/dma | |
parent | 88b53b9c1f2da681a5fb08c79437b8cd17b356ff (diff) | |
download | linux-3883dd74f0101d3ec94b213456c5965467ac8da9.tar.xz |
bindings: fsl-imx-sdma: Document 'fsl,sdma-event-remap' property
Document the 'fsl,sdma-event-remap' property and provide an example of
its usage.
Cc: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/dma')
-rw-r--r-- | Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt index dc8d3aa..175f0e4 100644 --- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt @@ -58,6 +58,15 @@ The third cell specifies the transfer priority as below. 1 Medium 2 Low +Optional properties: + +- gpr : The phandle to the General Purpose Register (GPR) node. +- fsl,sdma-event-remap : Register bits of sdma event remap, the format is + <reg shift val>. + reg is the GPR register offset. + shift is the bit position inside the GPR register. + val is the value of the bit (0 or 1). + Examples: sdma@83fb0000 { @@ -83,3 +92,21 @@ ssi2: ssi@70014000 { dma-names = "rx", "tx"; fsl,fifo-depth = <15>; }; + +Using the fsl,sdma-event-remap property: + +If we want to use SDMA on the SAI1 port on a MX6SX: + +&sdma { + gpr = <&gpr>; + /* SDMA events remap for SAI1_RX and SAI1_TX */ + fsl,sdma-event-remap = <0 15 1>, <0 16 1>; +}; + +The fsl,sdma-event-remap property in this case has two values: +- <0 15 1> means that the offset is 0, so GPR0 is the register of the +SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX. +Setting bit 15 to 1 selects SAI1_RX. +- <0 16 1> means that the offset is 0, so GPR0 is the register of the +SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX. +Setting bit 16 to 1 selects SAI1_TX. |