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author | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2014-03-17 00:02:46 (GMT) |
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committer | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2015-01-16 16:03:04 (GMT) |
commit | 4a93f21d87e769477c0cb2b98d7e7911b8d37c03 (patch) | |
tree | 0ebc255c0bc8a6a1d465473ca209cc86d48eb6b3 /Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt | |
parent | 9eca0a5875403027e10d68dd162df9790d42839e (diff) | |
download | linux-4a93f21d87e769477c0cb2b98d7e7911b8d37c03.tar.xz |
iommu/ipmmu-vmsa: Add device tree bindings documentation
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt')
-rw-r--r-- | Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt new file mode 100644 index 0000000..cd29083 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt @@ -0,0 +1,41 @@ +* Renesas VMSA-Compatible IOMMU + +The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables. +It provides address translation for bus masters outside of the CPU, each +connected to the IPMMU through a port called micro-TLB. + + +Required Properties: + + - compatible: Must contain "renesas,ipmmu-vmsa". + - reg: Base address and size of the IPMMU registers. + - interrupts: Specifiers for the MMU fault interrupts. For instances that + support secure mode two interrupts must be specified, for non-secure and + secure mode, in that order. For instances that don't support secure mode a + single interrupt must be specified. + + - #iommu-cells: Must be 1. + +Each bus master connected to an IPMMU must reference the IPMMU in its device +node with the following property: + + - iommus: A reference to the IPMMU in two cells. The first cell is a phandle + to the IPMMU and the second cell the number of the micro-TLB that the + device is connected to. + + +Example: R8A7791 IPMMU-MX and VSP1-D0 bus master + + ipmmu_mx: mmu@fe951000 { + compatible = "renasas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, + <0 221 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + }; + + vsp1@fe928000 { + ... + iommus = <&ipmmu_mx 13>; + ... + }; |