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author | Kishon Vijay Abraham I <kishon@ti.com> | 2015-12-21 08:54:10 (GMT) |
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committer | Kishon Vijay Abraham I <kishon@ti.com> | 2015-12-21 08:56:27 (GMT) |
commit | c396a1c7ee1b3b460cf01824b03e0627a7db5b01 (patch) | |
tree | 5f8b4ca9bedafa931b34a50177ae911d34227d8f /Documentation/devicetree/bindings/phy | |
parent | cc34ace73dfa24d9cda2fd2c4666e38a515a9052 (diff) | |
download | linux-c396a1c7ee1b3b460cf01824b03e0627a7db5b01.tar.xz |
phy: ti-pipe3: use *syscon* framework API to power on/off the PHY
Deprecate using phy-omap-control driver to power on/off the PHY and
use *syscon* framework to do the same.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/phy')
-rw-r--r-- | Documentation/devicetree/bindings/phy/ti-phy.txt | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt index 9cf9446..e06f980 100644 --- a/Documentation/devicetree/bindings/phy/ti-phy.txt +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt @@ -77,8 +77,6 @@ Required properties: * "div-clk" - apll clock Optional properties: - - ctrl-module : phandle of the control module used by PHY driver to power on - the PHY. - id: If there are multiple instance of the same type, in order to differentiate between each instance "id" can be used (e.g., multi-lane PCIe PHY). If "id" is not provided, it is set to default value of '1'. @@ -86,6 +84,14 @@ Optional properties: CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0 register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy. +Deprecated properties: + - ctrl-module : phandle of the control module used by PHY driver to power on + the PHY. + +Recommended properies: + - syscon-phy-power : phandle/offset pair. Phandle to the system control + module and the register offset to power on/off the PHY. + This is usually a subnode of ocp2scp to which it is connected. usb3phy@4a084400 { |