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author | Greg Kroah-Hartman <gregkh@suse.de> | 2011-02-18 20:11:27 (GMT) |
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committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-02-18 20:11:27 (GMT) |
commit | 80ae3fa5d6712ef3625eff617f72e190645d6361 (patch) | |
tree | fd9be0ecbb4baa6385aa1a75af7ced5f7d691be4 /Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt | |
parent | 59db5b2b9e0327e545ff5764dadcb26062c2ab1f (diff) | |
parent | 85e2efbb1db9a18d218006706d6e4fbeb0216213 (diff) | |
download | linux-80ae3fa5d6712ef3625eff617f72e190645d6361.tar.xz |
Merge 2.6.38-rc5 into staging-next
This is to resolve a merge conflict with:
drivers/staging/zram/zram_drv.c
as pointed out by Stephen Rothwell
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Nitin Gupta <ngupta@vflare.org>
Cc: Robert Jennings <rcj@linux.vnet.ibm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt')
-rw-r--r-- | Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt new file mode 100644 index 0000000..349f79f --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt @@ -0,0 +1,38 @@ +Every GPIO controller node must have #gpio-cells property defined, +this information will be used to translate gpio-specifiers. + +On CPM1 devices, all ports are using slightly different register layouts. +Ports A, C and D are 16bit ports and Ports B and E are 32bit ports. + +On CPM2 devices, all ports are 32bit ports and use a common register layout. + +Required properties: +- compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b", + "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d", + "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank" +- #gpio-cells : Should be two. The first cell is the pin number and the + second cell is used to specify optional parameters (currently unused). +- gpio-controller : Marks the port as GPIO controller. + +Example of three SOC GPIO banks defined as gpio-controller nodes: + + CPM1_PIO_A: gpio-controller@950 { + #gpio-cells = <2>; + compatible = "fsl,cpm1-pario-bank-a"; + reg = <0x950 0x10>; + gpio-controller; + }; + + CPM1_PIO_B: gpio-controller@ab8 { + #gpio-cells = <2>; + compatible = "fsl,cpm1-pario-bank-b"; + reg = <0xab8 0x10>; + gpio-controller; + }; + + CPM1_PIO_E: gpio-controller@ac8 { + #gpio-cells = <2>; + compatible = "fsl,cpm1-pario-bank-e"; + reg = <0xac8 0x18>; + gpio-controller; + }; |