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author | Greg Kroah-Hartman <gregkh@suse.de> | 2011-02-18 20:11:27 (GMT) |
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committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-02-18 20:11:27 (GMT) |
commit | 80ae3fa5d6712ef3625eff617f72e190645d6361 (patch) | |
tree | fd9be0ecbb4baa6385aa1a75af7ced5f7d691be4 /Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt | |
parent | 59db5b2b9e0327e545ff5764dadcb26062c2ab1f (diff) | |
parent | 85e2efbb1db9a18d218006706d6e4fbeb0216213 (diff) | |
download | linux-80ae3fa5d6712ef3625eff617f72e190645d6361.tar.xz |
Merge 2.6.38-rc5 into staging-next
This is to resolve a merge conflict with:
drivers/staging/zram/zram_drv.c
as pointed out by Stephen Rothwell
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Nitin Gupta <ngupta@vflare.org>
Cc: Robert Jennings <rcj@linux.vnet.ibm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt')
-rw-r--r-- | Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt new file mode 100644 index 0000000..bcc30ba --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt @@ -0,0 +1,36 @@ +* Freescale MSI interrupt controller + +Required properties: +- compatible : compatible list, contains 2 entries, + first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572, + etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on + the parent type. +- reg : should contain the address and the length of the shared message + interrupt register set. +- msi-available-ranges: use <start count> style section to define which + msi interrupt can be used in the 256 msi interrupts. This property is + optional, without this, all the 256 MSI interrupts can be used. +- interrupts : each one of the interrupts here is one entry per 32 MSIs, + and routed to the host interrupt controller. the interrupts should + be set as edge sensitive. +- interrupt-parent: the phandle for the interrupt controller + that services interrupts for this device. for 83xx cpu, the interrupts + are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed + to MPIC. + +Example: + msi@41600 { + compatible = "fsl,mpc8610-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; + }; |