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authorShaohui Xie <Shaohui.Xie@nxp.com>2016-09-13 08:09:55 (GMT)
committerXie Xiaobo <xiaobo.xie@nxp.com>2017-07-14 09:57:18 (GMT)
commitc6a783fd5d35714ea037c5736b9fd507b624b4ba (patch)
treeded860545f622778a8211e2fb53066c7e8ea2d8c /Documentation/devicetree/bindings
parent9004d8108e2ac77f0692bcf8691093d929104fbf (diff)
downloadlinux-c6a783fd5d35714ea037c5736b9fd507b624b4ba.tar.xz
dt-bindings: fsl: add LS1043A/LS1046A/LS2080A compatible for SCFG and DCFG
SCFG and DCFG are SoC-specific devices can be found on SoCs like LS1021A, LS1043A and LS1046A, this patch updates bindings for SCFG and DCFG to reflect more SoCs. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings')
-rw-r--r--Documentation/devicetree/bindings/arm/fsl.txt14
1 files changed, 11 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 2efbc09..a81277f 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -97,7 +97,7 @@ Freescale LS1021A Platform Device Tree Bindings
Required root node compatible properties:
- compatible = "fsl,ls1021a";
-Freescale LS1021A SoC-specific Device Tree Bindings
+Freescale SoC-specific Device Tree Bindings
-------------------------------------------
Freescale SCFG
@@ -105,7 +105,11 @@ Freescale SCFG
configuration and status registers for the chip. Such as getting PEX port
status.
Required properties:
- - compatible: should be "fsl,ls1021a-scfg"
+ - compatible: Should contain a chip-specific compatible string,
+ Chip-specific strings are of the form "fsl,<chip>-scfg",
+ The following <chip>s are known to be supported:
+ ls1021a, ls1043a, ls1046a, ls2080a.
+
- reg: should contain base address and length of SCFG memory-mapped registers
Example:
@@ -119,7 +123,11 @@ Freescale DCFG
configuration and status for the device. Such as setting the secondary
core start address and release the secondary core from holdoff and startup.
Required properties:
- - compatible: should be "fsl,ls1021a-dcfg"
+ - compatible: Should contain a chip-specific compatible string,
+ Chip-specific strings are of the form "fsl,<chip>-dcfg",
+ The following <chip>s are known to be supported:
+ ls1021a, ls1043a, ls1046a, ls2080a.
+
- reg : should contain base address and length of DCFG memory-mapped registers
Example: