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author | Heiko Stuebner <heiko@sntech.de> | 2016-03-24 21:29:01 (GMT) |
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committer | Kishon Vijay Abraham I <kishon@ti.com> | 2016-04-13 13:03:05 (GMT) |
commit | 0311c76e4722b8d6e5fa47eaee63c6552bcc74f5 (patch) | |
tree | 05a7ed06e2555976fb84bed21bb63451bf820244 /Documentation/devicetree | |
parent | f55532a0c0b8bb6148f4e07853b876ef73bc69ca (diff) | |
download | linux-0311c76e4722b8d6e5fa47eaee63c6552bcc74f5.tar.xz |
phy: rockchip-dp: should be a child device of the GRF
The displayport-phy is fully enclosed in the general register files (GRF).
Therefore as seen from the device-tree it shouldn't be a separate platform-
device but instead a sub-device of the GRF - using the simply-mfd mechanism.
The driver entered the kernel in the current merge-window, so we can still
adapt the binding without needing a fallback, as the binding hasn't been
released with a full kernel yet.
While the edp phy is fully part of the GRF, it doesn't have any separate
register set there, so doesn't get any register-area assigned.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r-- | Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt index 50c4f9b..e3b4809 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt @@ -8,15 +8,19 @@ Required properties: of memory mapped region. - clock-names: from common clock binding: Required elements: "24m" -- rockchip,grf: phandle to the syscon managing the "general register files" - #phy-cells : from the generic PHY bindings, must be 0; Example: -edp_phy: edp-phy { - compatible = "rockchip,rk3288-dp-phy"; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_EDP_24M>; - clock-names = "24m"; - #phy-cells = <0>; +grf: syscon@ff770000 { + compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; + +... + + edp_phy: edp-phy { + compatible = "rockchip,rk3288-dp-phy"; + clocks = <&cru SCLK_EDP_24M>; + clock-names = "24m"; + #phy-cells = <0>; + }; }; |