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author | David Wu <david.wu@rock-chips.com> | 2016-05-16 20:09:31 (GMT) |
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committer | Heiko Stuebner <heiko@sntech.de> | 2016-06-18 12:00:23 (GMT) |
commit | 69e5a8fe8c54e8d1579f1927ca8c30abeee8862d (patch) | |
tree | 8b1b6c2eef71701cf172629b903b205522b24a32 /Documentation/edac.txt | |
parent | 95c27ba7bd92febbd72a74658db1132f37a52d2f (diff) | |
download | linux-69e5a8fe8c54e8d1579f1927ca8c30abeee8862d.tar.xz |
arm64: dts: rockchip: add i2c nodes for rk3399
We've got 9 (count em!) i2c controllers on rk3399, some of which are in
the PMU power domain and some of which are normal peripherals. Add them
all to the main rk3399 dtsi file so future patches can turn them on in
the board dts files.
Note: by default we try to set the i2c clock rate to 200 MHz so that we
can achieve good i2c functional clock rates. 200 MHz gives us the
ability to make very close to 100 kHz / 400 kHz / 1 MHz rates. If
boards want to tune clock rates further they can always override.
Possibly boards could want to tune this if:
- they wanted to save an infinitesimal amount of power and they knew
their i2c bus was slow anyway. Since we gate the functional clock
when the i2c bus is not active, power savings would only be while i2c
transfers were happening and probably won't be very big anyway.
- they wanted to eek out a bit more speed by carefully tuning the source
clock to make divisions work out perfectly, accounting for the rise /
fall time measured on an actual board.
Note also that we still request 200 MHz for the PMU i2c busses even
though we expect that we won't make that exactly (currently PPLL is 676
MHz which gives us 169 MHz).
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
[dianders: wrote desc; put in assigned-clocks; reordered nodes]
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'Documentation/edac.txt')
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