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| author | Minghuan Lian <Minghuan.Lian@nxp.com> | 2017-01-17 06:38:32 (GMT) |
|---|---|---|
| committer | Xie Xiaobo <xiaobo.xie@nxp.com> | 2017-09-25 07:25:29 (GMT) |
| commit | 4026107b6dd6fcde49d0c958ac386383a3df60ee (patch) | |
| tree | 4434f7fa7857f70e047bf31d4379d7538e25970c /Documentation | |
| parent | fcc244eb4644b40467fdbc6f215fa05fc0416612 (diff) | |
| download | linux-4026107b6dd6fcde49d0c958ac386383a3df60ee.tar.xz | |
irqchip/ls-scfg-msi: add LS1046a MSI support
LS1046a includes 4 MSIRs, each MSIR is assigned a dedicate GIC
SPI interrupt and provides 32 MSI interrupts. Compared to previous
MSI, LS1046a's IBS(interrupt bit select) shift is changed to 2 and
total MSI interrupt number is changed to 128.
The patch adds structure 'ls_scfg_msir' to describe MSIR setting and
'ibs_shift' to store the different value between the SoCs.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions