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| author | Po Liu <po.liu@nxp.com> | 2017-05-22 07:46:02 (GMT) |
|---|---|---|
| committer | Xie Xiaobo <xiaobo.xie@nxp.com> | 2017-09-25 07:25:29 (GMT) |
| commit | 5be0fc5c16f3588d138aee7165f54abdb2fba01d (patch) | |
| tree | 87c5c806051f65d9a49ee73ad5bce751c97a24be /Documentation | |
| parent | 9c2aa654e19e2ac73bb89dc365e48e5b3e906f3f (diff) | |
| download | linux-5be0fc5c16f3588d138aee7165f54abdb2fba01d.tar.xz | |
pci:add support aer/pme interrupts with none MSI/MSI-X/INTx mode
[pcie part]
On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer/pme interrupts with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.
Signed-off-by: Po Liu <po.liu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/layerscape-pci.txt | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 41e9f55..51ed49e 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -18,8 +18,12 @@ Required properties: - reg: base addresses and lengths of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. -- interrupt-names: Must include the following entries: - "intr": The interrupt that is asserted for controller interrupts +- interrupt-names: It could include the following entries: + "aer": Asserted for aer interrupt when chip support the aer interrupt with + none MSI/MSI-X/INTx mode,but there is interrupt line for aer. + "pme": Asserted for pme interrupt when chip support the pme interrupt with + none MSI/MSI-X/INTx mode,but there is interrupt line for pme. + ...... - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node The second entry must be '0' or '1' based on physical PCIe controller index. @@ -35,8 +39,9 @@ Example: reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ - interrupt-names = "intr"; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, /* aer interrupt */ + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* pme interrupt */ + interrupt-names = "aer", "pme"; fsl,pcie-scfg = <&scfg 0>; #address-cells = <3>; #size-cells = <2>; |