Merge branch 'linux-4.9-nxp' into linux-4.9 on Dec. 8, 2017

Signed-off-by: Xiaobo Xie <xiaobo.xie@nxp.com>

4 files changed, 178 insertions, 1 deletions

diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
index 49ccabb..a4ff93d 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
@@ -8,6 +8,7 @@ Required properties:
               "fsl,ls1043a-msi"
               "fsl,ls1046a-msi"
               "fsl,ls1043a-v1.1-msi"
+              "fsl,ls1012a-msi"
 - msi-controller: indicates that this is a PCIe MSI controller node
 - reg: physical base address of the controller and length of memory mapped.
 - interrupts: an interrupt to the parent interrupt controller.
diff --git a/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt b/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt
new file mode 100644
index 0000000..780de44
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt
@@ -0,0 +1,173 @@
+=============================================================================
+NXP Programmable Packet Forwarding Engine Device Bindings
+
+CONTENTS
+  - PFE Node
+  - Ethernet Node
+
+=============================================================================
+PFE Node
+
+DESCRIPTION
+
+PFE Node has all the properties associated with Packet Forwarding Engine block.
+
+PROPERTIES
+
+- compatible
+		Usage: required
+		Value type: <stringlist>
+		Definition: Must include "fsl,pfe"
+
+- reg
+		Usage: required
+		Value type: <prop-encoded-array>
+		Definition: A standard property.
+		Specifies the offset of the following registers:
+		- PFE configuration registers
+		- DDR memory used by PFE
+
+- fsl,pfe-num-interfaces
+		Usage: required
+		Value type: <u32>
+		Definition: Must be present. Value can be either one or two.
+
+- interrupts
+		Usage: required
+		Value type: <prop-encoded-array>
+		Definition: Three interrupts are specified in this property.
+		- HIF interrupt
+		- HIF NO COPY interrupt
+		- Wake On LAN interrupt
+
+- interrupt-names
+		Usage: required
+		Value type: <stringlist>
+		Definition: Following strings are defined for the 3 interrupts.
+		"pfe_hif" - HIF interrupt
+		"pfe_hif_nocpy" - HIF NO COPY interrupt
+		"pfe_wol" - Wake On LAN interrupt
+
+- memory-region
+		Usage: required
+		Value type: <phandle>
+		Definition: phandle to a node describing reserved memory used by pfe.
+		Refer:- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
+
+- fsl,pfe-scfg
+		Usage: required
+		Value type: <phandle>
+		Definition: phandle for scfg.
+
+- fsl,rcpm-wakeup
+		Usage: required
+		Value type: <phandle>
+		Definition: phandle for rcpm.
+
+- clocks
+		Usage: required
+		Value type: <phandle>
+		Definition: phandle for clockgen.
+
+- clock-names
+		Usage: required
+		Value type: <string>
+		Definition: phandle for clock name.
+
+EXAMPLE
+
+pfe: pfe@04000000 {
+	compatible = "fsl,pfe";
+	reg =   <0x0 0x04000000 0x0 0xc00000>,	/* AXI 16M */
+		<0x0 0x83400000 0x0 0xc00000>;  /* PFE DDR 12M */
+	reg-names = "pfe", "pfe-ddr";
+	fsl,pfe-num-interfaces = <0x2>;
+	interrupts = <0 172 0x4>,    /* HIF interrupt */
+		     <0 173 0x4>,    /*HIF_NOCPY interrupt */
+		     <0 174 0x4>;    /* WoL interrupt */
+	interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
+	memory-region = <&pfe_reserved>;
+	fsl,pfe-scfg = <&scfg 0>;
+	fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
+	clocks = <&clockgen 4 0>;
+	clock-names = "pfe";
+
+	status = "okay";
+	pfe_mac0: ethernet@0 {
+	};
+
+	pfe_mac1: ethernet@1 {
+	};
+};
+
+=============================================================================
+Ethernet Node
+
+DESCRIPTION
+
+Ethernet Node has all the properties associated with PFE used by platforms to
+connect to PHY:
+
+PROPERTIES
+
+- compatible
+		Usage: required
+		Value type: <stringlist>
+		Definition: Must include "fsl,pfe-gemac-port"
+
+- reg
+		Usage: required
+		Value type: <prop-encoded-array>
+		Definition: A standard property.
+		Specifies the gemacid of the interface.
+
+- fsl,gemac-bus-id
+		Usage: required
+		Value type: <u32>
+		Definition: Must be present. Value should be the id of the bus
+		connected to gemac.
+
+- fsl,gemac-phy-id
+		Usage: required
+		Value type: <u32>
+		Definition: Must be present. Value should be the id of the phy
+		connected to gemac.
+
+- fsl,mdio-mux-val
+		Usage: required
+		Value type: <u32>
+		Definition: Must be present. Value can be either 0 or 2 or 3.
+		This value is used to configure the mux to enable mdio.
+
+- phy-mode
+		Usage: required
+		Value type: <string>
+		Definition: Must include "sgmii"
+
+- fsl,pfe-phy-if-flags
+		Usage: required
+		Value type: <u32>
+		Definition: Must be present. Value should be 0 by default.
+		If there is not phy connected, this need to be 1.
+
+- mdio
+		optional subnode that specifies the mdio bus. This has reg
+		property which is used to enable/disable the mdio bus.
+
+EXAMPLE
+
+ethernet@0 {
+	compatible = "fsl,pfe-gemac-port";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	reg = <0x0>;	/* GEM_ID */
+	fsl,gemac-bus-id = <0x0>;	/* BUS_ID */
+	fsl,gemac-phy-id = <0x2>;	/* PHY_ID */
+	fsl,mdio-mux-val = <0x0>;
+	phy-mode = "sgmii";
+	fsl,pfe-phy-if-flags = <0x0>;
+
+	mdio@0 {
+		reg = <0x1>; /* enabled/disabled */
+	};
+};
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 6f547b2..38cf657 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -15,7 +15,8 @@ Required properties:
 - compatible: should contain the platform identifier such as:
         "fsl,ls1021a-pcie", "snps,dw-pcie"
         "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
-        "fsl,ls2088a-pcie", "fsl,ls1088a-pcie"
+        "fsl,ls2088a-pcie"
+        "fsl,ls1088a-pcie"
         "fsl,ls1046a-pcie"
         "fsl,ls1012a-pcie"
 - reg: base addresses and lengths of the PCIe controller
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 89c399f..f4b8973 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -45,6 +45,8 @@ Optional properties:
 			a free-running PHY clock.
  - snps,dis-del-phy-power-chg-quirk: when set core will change PHY power
 			from P0 to P1/P2/P3 without delay.
+ - snps,disable_devinit_u1u2: when set, disable device-initiated U1/U2
+			LPM request in USB device mode.
  - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
 			utmi_l1_suspend_n, false when asserts utmi_sleep_n
  - snps,hird-threshold: HIRD threshold