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author | Frank Arnold <frank.arnold@amd.com> | 2011-05-16 13:39:47 (GMT) |
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committer | H. Peter Anvin <hpa@linux.intel.com> | 2011-05-16 18:24:27 (GMT) |
commit | 42be450565b0fc4607fae3e3a7da038d367a23ed (patch) | |
tree | b6b42606ee23185c14414c459ddcd43e9d0777a0 /Documentation | |
parent | 50e7534427283afd997d58481778c07bea79eb63 (diff) | |
download | linux-42be450565b0fc4607fae3e3a7da038d367a23ed.tar.xz |
x86, AMD, cacheinfo: Fix L3 cache index disable checks
We provide two slots to disable cache indices, and have a check to
prevent both slots to be used for the same index.
If the user disables the same index on different subcaches, both slots
will hold the same index, e.g.
$ echo 2047 > /sys/devices/system/cpu/cpu0/cache/index3/cache_disable_0
$ cat /sys/devices/system/cpu/cpu0/cache/index3/cache_disable_0
2047
$ echo 1050623 > /sys/devices/system/cpu/cpu0/cache/index3/cache_disable_1
$ cat /sys/devices/system/cpu/cpu0/cache/index3/cache_disable_1
2047
due to the fact that the check was looking only at index bits [11:0]
and was ignoring writes to bits outside that range. The more correct
fix is to simply check whether the index is within the bounds of
[0..l3->indices].
While at it, cleanup comments and drop now-unused local macros.
Signed-off-by: Frank Arnold <frank.arnold@amd.com>
Link: http://lkml.kernel.org/r/1305553188-21061-3-git-send-email-bp@amd64.org
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions