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| author | Vineet Gupta <vgupta@synopsys.com> | 2013-06-15 04:51:51 (GMT) |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2013-06-22 08:16:43 (GMT) |
| commit | 30499186602afa1d62c2e5d354d02214a0ee00b7 (patch) | |
| tree | d0e928b54b995702822c70a32b3479625ff30c1f /arch/arc/include/asm/cache.h | |
| parent | 6546415226f2fc3ab0a820464774e02a1679f90a (diff) | |
| download | linux-30499186602afa1d62c2e5d354d02214a0ee00b7.tar.xz | |
ARC: cache detection code bitrot
* Number of (i|d)cache ways can be retrieved from BCRs and hence no need
to cross check with with built-in constants
* Use of IS_ENABLED() to check for a Kconfig option
* is_not_cache_aligned() not used anymore
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/include/asm/cache.h')
| -rw-r--r-- | arch/arc/include/asm/cache.h | 11 |
1 files changed, 1 insertions, 10 deletions
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 44eb07e..5802849 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -18,22 +18,13 @@ #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -#define ARC_ICACHE_WAYS 2 -#define ARC_DCACHE_WAYS 4 - -/* Helpers */ +/* For a rare case where customers have differently config I/D */ #define ARC_ICACHE_LINE_LEN L1_CACHE_BYTES #define ARC_DCACHE_LINE_LEN L1_CACHE_BYTES #define ICACHE_LINE_MASK (~(ARC_ICACHE_LINE_LEN - 1)) #define DCACHE_LINE_MASK (~(ARC_DCACHE_LINE_LEN - 1)) -#if ARC_ICACHE_LINE_LEN != ARC_DCACHE_LINE_LEN -#error "Need to fix some code as I/D cache lines not same" -#else -#define is_not_cache_aligned(p) ((unsigned long)p & (~DCACHE_LINE_MASK)) -#endif - /* * ARC700 doesn't cache any access in top 256M. * Ideal for wiring memory mapped peripherals as we don't need to do |