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| author | Vineet Gupta <vgupta@synopsys.com> | 2015-04-03 09:37:07 (GMT) |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2015-06-25 00:30:19 (GMT) |
| commit | 795f4558562fd5318260d5d8144a2f8612aeda7b (patch) | |
| tree | b4cb8211acf56f2f8acc7ef1429cee4e667f2834 /arch/arc/include | |
| parent | a5c8b52abe677977883655166796f167ef1e0084 (diff) | |
| download | linux-795f4558562fd5318260d5d8144a2f8612aeda7b.tar.xz | |
ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)
L2 cache on ARCHS processors is called SLC (System Level Cache)
For working DMA (in absence of hardware assisted IO Coherency) we need
to manage SLC explicitly when buffers transition between cpu and
controllers.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/include')
| -rw-r--r-- | arch/arc/include/asm/cache.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index d21c76d..d67345d 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -82,5 +82,16 @@ extern void read_decode_cache_bcr(void); /*System-level cache (L2 cache) related Auxiliary registers */ #define ARC_REG_SLC_CFG 0x901 +#define ARC_REG_SLC_CTRL 0x903 +#define ARC_REG_SLC_FLUSH 0x904 +#define ARC_REG_SLC_INVALIDATE 0x905 +#define ARC_REG_SLC_RGN_START 0x914 +#define ARC_REG_SLC_RGN_END 0x916 + +/* Bit val in SLC_CONTROL */ +#define SLC_CTRL_IM 0x040 +#define SLC_CTRL_DISABLE 0x001 +#define SLC_CTRL_BUSY 0x100 +#define SLC_CTRL_RGN_OP_INV 0x200 #endif /* _ASM_CACHE_H */ |