summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/exynos5422-cpus.dtsi
diff options
context:
space:
mode:
authorKrzysztof Kozlowski <k.kozlowski@samsung.com>2016-02-18 05:13:02 (GMT)
committerKrzysztof Kozlowski <k.kozlowski@samsung.com>2016-03-01 09:03:42 (GMT)
commit3b93fc0f2a1f646745de8738f04fd3568b948197 (patch)
treeebbc2cfe54e2141738996c5456eaf46bb6a95e56 /arch/arm/boot/dts/exynos5422-cpus.dtsi
parent65ebf53fbda8adb2c4a10a8d1dd8cff4b9513021 (diff)
downloadlinux-3b93fc0f2a1f646745de8738f04fd3568b948197.tar.xz
ARM: dts: exynos: Add cooling levels for Exynos5422/5800 CPUs
On Exynos5422 and Exynos5800 we support 12 cpufreq steps (200-1300 MHz) for LITTLE and 18 steps for big core (200-1700 MHz). Add respective cooling cells. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/exynos5422-cpus.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos5422-cpus.dtsi24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index 9b46b9f..bf3c6f1 100644
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -32,6 +32,9 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
+ cooling-min-level = <0>;
+ cooling-max-level = <11>;
+ #cooling-cells = <2>; /* min followed by max */
};
cpu1: cpu@101 {
@@ -41,6 +44,9 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
+ cooling-min-level = <0>;
+ cooling-max-level = <11>;
+ #cooling-cells = <2>; /* min followed by max */
};
cpu2: cpu@102 {
@@ -50,6 +56,9 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
+ cooling-min-level = <0>;
+ cooling-max-level = <11>;
+ #cooling-cells = <2>; /* min followed by max */
};
cpu3: cpu@103 {
@@ -59,6 +68,9 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
+ cooling-min-level = <0>;
+ cooling-max-level = <11>;
+ #cooling-cells = <2>; /* min followed by max */
};
cpu4: cpu@0 {
@@ -69,6 +81,9 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
+ cooling-min-level = <0>;
+ cooling-max-level = <15>;
+ #cooling-cells = <2>; /* min followed by max */
};
cpu5: cpu@1 {
@@ -78,6 +93,9 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
+ cooling-min-level = <0>;
+ cooling-max-level = <15>;
+ #cooling-cells = <2>; /* min followed by max */
};
cpu6: cpu@2 {
@@ -87,6 +105,9 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
+ cooling-min-level = <0>;
+ cooling-max-level = <15>;
+ #cooling-cells = <2>; /* min followed by max */
};
cpu7: cpu@3 {
@@ -96,6 +117,9 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
+ cooling-min-level = <0>;
+ cooling-max-level = <15>;
+ #cooling-cells = <2>; /* min followed by max */
};
};
};