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| author | Vladimir Zapolskiy <vz@mleia.com> | 2015-10-17 21:35:53 (GMT) |
|---|---|---|
| committer | Vladimir Zapolskiy <vz@mleia.com> | 2015-11-18 16:01:08 (GMT) |
| commit | 2a6c6563313dd5c96277e4a3368df65e268bcc9b (patch) | |
| tree | 318801b0fe4745eebc29ec047d39388a66c80514 /arch/arm/boot/dts/lpc32xx.dtsi | |
| parent | 246d8fc33e570b7c1e69cdbf395fcfcee58785cc (diff) | |
| download | linux-2a6c6563313dd5c96277e4a3368df65e268bcc9b.tar.xz | |
arm: dts: lpc32xx: add device node for the second pwm controller
LPC32xx SoCs have two independent PWM controllers, they have different
clock parents, clock gates and even slightly different controls,
each of these two PWM controllers has one output channel. Due to
almost similar controls arranged in a row it is incorrectly assumed
that there is one PWM controller with two channels, fix this problem
in lpc32xx.dtsi, which at the moment prevents separate configuration
of different clock parents and gates for both PWM controllers.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Diffstat (limited to 'arch/arm/boot/dts/lpc32xx.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/lpc32xx.dtsi | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index fb0e9ae..be82992 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -290,9 +290,15 @@ status = "disabled"; }; - pwm: pwm@4005C000 { + pwm1: pwm@4005C000 { compatible = "nxp,lpc3220-pwm"; - reg = <0x4005C000 0x8>; + reg = <0x4005C000 0x4>; + status = "disabled"; + }; + + pwm2: pwm@4005C004 { + compatible = "nxp,lpc3220-pwm"; + reg = <0x4005C004 0x4>; status = "disabled"; }; }; |