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author | Stephen Warren <swarren@nvidia.com> | 2013-08-09 14:49:29 (GMT) |
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committer | Stephen Warren <swarren@nvidia.com> | 2013-08-12 20:20:36 (GMT) |
commit | 44fefab459cfb78c446a8b7cc4bbf622d5b97396 (patch) | |
tree | 4cb4d0535b02887b879ab3996445b5279131e2bc /arch/arm/boot/dts/tegra30.dtsi | |
parent | bb034cb5eb7fa6596c40d405e31cef02de21ad30 (diff) | |
download | linux-44fefab459cfb78c446a8b7cc4bbf622d5b97396.tar.xz |
ARM: tegra: Fix Beaver's PCIe lane configuration
Beaver's PCIe lane configuration most closely matches x2 x2 x2 rather
than x4 x1 x1, since clocks 0 and 2 are used, and lanes 0 and 5 are used,
and the only way those align is with a x2 x2 x2 configuration.
Also, disable root port 1; there's nothing connected to it. Root port 0
is the on-board PCIe Ethernet, and port 2 is the mini-PCIe slot.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30.dtsi')
0 files changed, 0 insertions, 0 deletions