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authorArnd Bergmann <arnd@arndb.de>2014-03-27 01:10:57 (GMT)
committerArnd Bergmann <arnd@arndb.de>2014-03-27 01:19:41 (GMT)
commit32adc19d4b2f2d9a26fbbd0c1744d5b313106d6a (patch)
tree5e034ff3b39b6495a4d1d2cc3839b985b2e711d0 /arch/arm/boot/dts
parent22673b71689a65a89335d0f3e42ce952efb3e7e1 (diff)
parent1a259251f3638b04c1dbe07220958af9572c95bb (diff)
downloadlinux-32adc19d4b2f2d9a26fbbd0c1744d5b313106d6a.tar.xz
Merge tag 'zynq-cleanup-for-3.15-v2' of git://git.xilinx.com/linux-xlnx into next/cleanup2
Merge "arm: Xilinx Zynq cleanup patches for v3.15" from Michal Simek: - Redesign SLCR initialization to enable driver developing which targets SLCR space * tag 'zynq-cleanup-for-3.15-v2' of git://git.xilinx.com/linux-xlnx: ARM: zynq: Add waituart implementation ARM: zynq: Move of_clk_init from clock driver ARM: zynq: Introduce zynq_slcr_unlock() ARM: zynq: Add and use zynq_slcr_read/write() helper functions ARM: zynq: Make zynq_slcr_base static ARM: zynq: Map I/O memory on clkc init ARM: zynq: Hang iomapped slcr address on device_node ARM: zynq: Split slcr in two parts ARM: zynq: Move clock_init from slcr to common arm: dt: zynq: Add fclk-enable property to clkc node [Arnd: remove SOC_BUS support from pull request] Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi43
1 files changed, 21 insertions, 22 deletions
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 8b67b19..602e12e 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -123,29 +123,28 @@
} ;
slcr: slcr@f8000000 {
- compatible = "xlnx,zynq-slcr";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,zynq-slcr", "syscon";
reg = <0xF8000000 0x1000>;
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- clkc: clkc {
- #clock-cells = <1>;
- compatible = "xlnx,ps7-clkc";
- ps-clk-frequency = <33333333>;
- clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
- "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
- "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
- "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
- "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
- "dma", "usb0_aper", "usb1_aper", "gem0_aper",
- "gem1_aper", "sdio0_aper", "sdio1_aper",
- "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
- "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
- "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
- "dbg_trc", "dbg_apb";
- };
+ ranges;
+ clkc: clkc@100 {
+ #clock-cells = <1>;
+ compatible = "xlnx,ps7-clkc";
+ ps-clk-frequency = <33333333>;
+ fclk-enable = <0>;
+ clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+ "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
+ "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
+ "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+ "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+ "dma", "usb0_aper", "usb1_aper", "gem0_aper",
+ "gem1_aper", "sdio0_aper", "sdio1_aper",
+ "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+ "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
+ "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
+ "dbg_trc", "dbg_apb";
+ reg = <0x100 0x100>;
};
};