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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2011-03-28 13:57:46 (GMT)
committerWill Deacon <will.deacon@arm.com>2011-05-11 15:04:17 (GMT)
commit6ac77e469e991e9dd91b28e503fa24b5609eedba (patch)
tree68c0b58456e2e5524624ca48a8f8c2a77b7d99c5 /arch/arm/configs
parent1a01753ed90a4fb84357b9b592e50564c07737f7 (diff)
downloadlinux-6ac77e469e991e9dd91b28e503fa24b5609eedba.tar.xz
ARM: GIC: Convert GIC library to use the IO relaxed operations
The GIC register accesses today make use of readl()/writel() which prove to be very expensive when used along with mandatory barriers. This mandatory barriers also introduces an un-necessary and expensive l2x0_sync() operation. On Cortex-A9 MP cores, GIC IO accesses from CPU are direct and doesn't go through L2X0 write buffer. A DSB before writel_relaxed() in gic_raise_softirq() is added to be compliant with the Barrier Litmus document - the mailbox scenario. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com>
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