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| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-09-25 14:39:20 (GMT) |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-09-25 14:39:20 (GMT) |
| commit | 2b4ae1f1d2ae595ff2fc5597287881796e0e6bfc (patch) | |
| tree | a572cd8d4044bfa234e51a4fe04199e9b32c8181 /arch/arm/kernel | |
| parent | c0e9587841a0fd79bbf8296034faefb9afe72fb4 (diff) | |
| download | linux-2b4ae1f1d2ae595ff2fc5597287881796e0e6bfc.tar.xz | |
[ARM] Print details relevant to how we handle the cache
This replaces the original cache type decoding printks. We now
indicate how we're treating the cache which we found, rather
than what we found.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/kernel')
| -rw-r--r-- | arch/arm/kernel/setup.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 5b121d8..2f5d364 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -248,6 +248,15 @@ static void __init cacheid_init(void) } else { cacheid = CACHEID_VIVT; } + + printk("CPU: %s data cache, %s instruction cache\n", + cache_is_vivt() ? "VIVT" : + cache_is_vipt_aliasing() ? "VIPT aliasing" : + cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown", + cache_is_vivt() ? "VIVT" : + icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" : + cache_is_vipt_aliasing() ? "VIPT aliasing" : + cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown"); } /* |