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| author | Marc Zyngier <marc.zyngier@arm.com> | 2013-06-21 12:08:47 (GMT) |
|---|---|---|
| committer | Christoffer Dall <christoffer.dall@linaro.org> | 2013-06-26 17:50:04 (GMT) |
| commit | 479c5ae2f8a55509b691494cd13691d3dc31d102 (patch) | |
| tree | 6892951511aa62357eec0266f1dc6ca1d4bc9652 /arch/arm/kvm/interrupts.S | |
| parent | 6a077e4ab9cbfbf279fb955bae05b03781c97013 (diff) | |
| download | linux-479c5ae2f8a55509b691494cd13691d3dc31d102.tar.xz | |
ARM: KVM: add missing dsb before invalidating Stage-2 TLBs
When performing a Stage-2 TLB invalidation, it is necessary to
make sure the write to the page tables is observable by all CPUs.
For this purpose, add a dsb instruction to __kvm_tlb_flush_vmid_ipa
before doing the TLB invalidation itself.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Diffstat (limited to 'arch/arm/kvm/interrupts.S')
| -rw-r--r-- | arch/arm/kvm/interrupts.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S index d0a8fa3..20e03d9 100644 --- a/arch/arm/kvm/interrupts.S +++ b/arch/arm/kvm/interrupts.S @@ -49,6 +49,7 @@ __kvm_hyp_code_start: ENTRY(__kvm_tlb_flush_vmid_ipa) push {r2, r3} + dsb ishst add r0, r0, #KVM_VTTBR ldrd r2, r3, [r0] mcrr p15, 6, r2, r3, c2 @ Write VTTBR |