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authorNicolas Ferre <nicolas.ferre@atmel.com>2010-10-22 16:55:39 (GMT)
committerNicolas Ferre <nicolas.ferre@atmel.com>2010-10-26 09:32:48 (GMT)
commita2a571b74a3881963d8d09deb272d13afe5b49e3 (patch)
tree491cf5ff56293287906f9cfec785345f24cd2180 /arch/arm/mach-at91/pm.h
parent8aeeda822fbfe7da2d4ea391a9757e9532796598 (diff)
downloadlinux-a2a571b74a3881963d8d09deb272d13afe5b49e3.tar.xz
AT91: pm: make sure that r0 is 0 when dealing with cache operations
When using CP15 cache operations (c7), we make sure that Rd (r0) is actually 0 as ARM 926 TRM is saying. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91/pm.h')
-rw-r--r--arch/arm/mach-at91/pm.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 2c4424b..ce9a206 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -21,7 +21,8 @@ static inline u32 sdram_selfrefresh_enable(void)
}
#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
-#define wait_for_interrupt_enable() asm("mcr p15, 0, r0, c7, c0, 4")
+#define wait_for_interrupt_enable() asm volatile ("mcr p15, 0, %0, c7, c0, 4" \
+ : : "r" (0))
#elif defined(CONFIG_ARCH_AT91CAP9)
#include <mach/at91cap9_ddrsdr.h>