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authorShawn Guo <shawn.guo@freescale.com>2014-09-12 02:40:28 (GMT)
committerShawn Guo <shawn.guo@freescale.com>2014-09-16 02:09:40 (GMT)
commit69d9a3fe06ed4bdb69f0a20cfa031dbcb0ee8dc3 (patch)
tree20264f9f8342f8b2f7c16b7a5a8a6e2eb984719b /arch/arm/mach-imx/clk-imx6q.c
parentdbaf381ffbf3acd4ac9a987f567a2b1a5edf6e62 (diff)
downloadlinux-69d9a3fe06ed4bdb69f0a20cfa031dbcb0ee8dc3.tar.xz
ARM: imx: fix register offset of pll7_usb_host gate clock
There is a copy&paste error on register offset of pll7_usb_host gate clock introduced by i.MX6 PLL bypass support patches. The error breaks the ENET function, because it overwrites the pll6_enet gate bit. Correct the offset for all i.MX6 clock drivers. Thanks to Fugang Duan <B38611@freescale.com> for spotting the error. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx/clk-imx6q.c')
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4ee6e77..4f8ce60 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -187,7 +187,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
- clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0xe0, 13);
+ clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
/*
* Bit 20 is the reserved and read-only bit, we do this only for: