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| author | Juergen Beisert <jbe@pengutronix.de> | 2010-09-22 07:42:15 (GMT) |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-10-11 13:31:39 (GMT) |
| commit | 9524705c867dc8d5b558f4793b7464eab967a530 (patch) | |
| tree | 03b5e330f23d1c7b2b01959eb886678304c5b222 /arch/arm/mach-mx3 | |
| parent | 55fd2ef6d9e9f40f30d891e01f2f565552e688fa (diff) | |
| download | linux-9524705c867dc8d5b558f4793b7464eab967a530.tar.xz | |
MX35: Fix bogus L2 cache settings
i.MX35 CPUs marked with "MCIMX357CJQ5C M99V CTHA0943B" are coming with bogus
L2 cache settings. If these settings are kept unmodified prior enabling the L2
cache the CPU runs amok immediately when its enabled.
This fix should not hurt already working CPUs, as they are using the written
register value already.
Its currently unknown if its possible to detect the production lot from the
software to fix only affected CPUs.
While at it, make sure that mxc_init_l2x0 is only executed on i.MX31/35
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mx3')
| -rw-r--r-- | arch/arm/mach-mx3/mm.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c index 20e48c0..b4ffc53 100644 --- a/arch/arm/mach-mx3/mm.c +++ b/arch/arm/mach-mx3/mm.c @@ -110,6 +110,24 @@ void __init mx35_init_irq(void) static int mxc_init_l2x0(void) { void __iomem *l2x0_base; + void __iomem *clkctl_base; +/* + * First of all, we must repair broken chip settings. There are some + * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These + * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. + * Workaraound is to setup the correct register setting prior enabling the + * L2 cache. This should not hurt already working CPUs, as they are using the + * same value + */ +#define L2_MEM_VAL 0x10 + + clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); + if (clkctl_base != NULL) { + writel(0x00000515, clkctl_base + L2_MEM_VAL); + iounmap(clkctl_base); + } else { + pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); + } l2x0_base = ioremap(L2CC_BASE_ADDR, 4096); if (IS_ERR(l2x0_base)) { |