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authorTony Lindgren <tony@atomide.com>2010-02-15 17:27:25 (GMT)
committerTony Lindgren <tony@atomide.com>2010-02-15 17:27:25 (GMT)
commit4751227df948582e82f19df30efa662ab71fa980 (patch)
treefcaa71e589feedf607377881109088b6eba50822 /arch/arm/mach-omap2/clock44xx_data.c
parent61a07c80a7cf7333475e7eda9934dac9a8a9c8b9 (diff)
downloadlinux-4751227df948582e82f19df30efa662ab71fa980.tar.xz
omap3/4: Fix compile for multi-omap for clkops_noncore_dpll_ops
Rename clkops_noncore_dpll_ops for omap3 and omap4. Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock44xx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 35ffe63..86af31d 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -279,7 +279,7 @@ static struct clk dpll_abe_ck = {
.parent = &abe_dpll_refclk_mux_ck,
.dpll_data = &dpll_abe_dd,
.init = &omap2_init_dpll_parent,
- .ops = &clkops_noncore_dpll_ops,
+ .ops = &omap4_clkops_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
@@ -668,7 +668,7 @@ static struct clk dpll_iva_ck = {
.parent = &dpll_sys_ref_clk,
.dpll_data = &dpll_iva_dd,
.init = &omap2_init_dpll_parent,
- .ops = &clkops_noncore_dpll_ops,
+ .ops = &omap4_clkops_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
@@ -731,7 +731,7 @@ static struct clk dpll_mpu_ck = {
.parent = &dpll_sys_ref_clk,
.dpll_data = &dpll_mpu_dd,
.init = &omap2_init_dpll_parent,
- .ops = &clkops_noncore_dpll_ops,
+ .ops = &omap4_clkops_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
@@ -807,7 +807,7 @@ static struct clk dpll_per_ck = {
.parent = &dpll_sys_ref_clk,
.dpll_data = &dpll_per_dd,
.init = &omap2_init_dpll_parent,
- .ops = &clkops_noncore_dpll_ops,
+ .ops = &omap4_clkops_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
@@ -930,7 +930,7 @@ static struct clk dpll_unipro_ck = {
.parent = &dpll_sys_ref_clk,
.dpll_data = &dpll_unipro_dd,
.init = &omap2_init_dpll_parent,
- .ops = &clkops_noncore_dpll_ops,
+ .ops = &omap4_clkops_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
@@ -988,7 +988,7 @@ static struct clk dpll_usb_ck = {
.parent = &dpll_sys_ref_clk,
.dpll_data = &dpll_usb_dd,
.init = &omap2_init_dpll_parent,
- .ops = &clkops_noncore_dpll_ops,
+ .ops = &omap4_clkops_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,