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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-14 23:06:58 (GMT) |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-14 23:06:58 (GMT) |
| commit | 85082fd7cbe3173198aac0eb5e85ab1edcc6352c (patch) | |
| tree | edbc09b7945994f78668d218fa02e991c3b3b365 /arch/arm/mach-omap2/cm.h | |
| parent | 666484f0250db2e016948d63b3ef33e202e3b8d0 (diff) | |
| parent | 53ffe3b440aa85af6fc4eda09b2d44bcdd312d4d (diff) | |
| download | linux-85082fd7cbe3173198aac0eb5e85ab1edcc6352c.tar.xz | |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (241 commits)
[ARM] 5171/1: ep93xx: fix compilation of modules using clocks
[ARM] 5133/2: at91sam9g20 defconfig file
[ARM] 5130/4: Support for the at91sam9g20
[ARM] 5160/1: IOP3XX: gpio/gpiolib support
[ARM] at91: Fix NAND FLASH timings for at91sam9x evaluation kits.
[ARM] 5084/1: zylonite: Register AC97 device
[ARM] 5085/2: PXA: Move AC97 over to the new central device declaration model
[ARM] 5120/1: pxa: correct platform driver names for PXA25x and PXA27x UDC drivers
[ARM] 5147/1: pxaficp_ir: drop pxa_gpio_mode calls, as pin setting
[ARM] 5145/1: PXA2xx: provide api to control IrDA pins state
[ARM] 5144/1: pxaficp_ir: cleanup includes
[ARM] pxa: remove pxa_set_cken()
[ARM] pxa: allow clk aliases
[ARM] Feroceon: don't disable BPU on boot
[ARM] Orion: LED support for HP mv2120
[ARM] Orion: add RD88F5181L-FXO support
[ARM] Orion: add RD88F5181L-GE support
[ARM] Orion: add Netgear WNR854T support
[ARM] s3c2410_defconfig: update for current build
[ARM] Acer n30: Minor style and indentation fixes.
...
Diffstat (limited to 'arch/arm/mach-omap2/cm.h')
| -rw-r--r-- | arch/arm/mach-omap2/cm.h | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index 8489f30..87a44c7 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -81,6 +81,7 @@ #define OMAP3430ES2_CM_FCLKEN3 0x0008 #define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 #define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 +#define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2 #define OMAP3430_CM_CLKSEL1 CM_CLKSEL #define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL #define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 @@ -96,15 +97,21 @@ /* Clock management domain register get/set */ #ifndef __ASSEMBLER__ -static inline void cm_write_mod_reg(u32 val, s16 module, s16 idx) + +extern u32 cm_read_mod_reg(s16 module, u16 idx); +extern void cm_write_mod_reg(u32 val, s16 module, u16 idx); +extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); + +static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) { - __raw_writel(val, OMAP_CM_REGADDR(module, idx)); + return cm_rmw_mod_reg_bits(bits, bits, module, idx); } -static inline u32 cm_read_mod_reg(s16 module, s16 idx) +static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) { - return __raw_readl(OMAP_CM_REGADDR(module, idx)); + return cm_rmw_mod_reg_bits(bits, 0x0, module, idx); } + #endif /* CM register bits shared between 24XX and 3430 */ |