diff options
author | Mark A. Greer <mgreer@animalcreek.com> | 2012-12-21 16:28:14 (GMT) |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2013-03-30 21:52:17 (GMT) |
commit | 1cb804b93f506dfba5fd684a8ea63706aaa8e709 (patch) | |
tree | 04470ee35b3583477ba51ee6cddd24a6fc95f2d8 /arch/arm/mach-omap2/omap_hwmod_33xx_data.c | |
parent | ff2acd7d5da9c78ad6ffb7663c5d72d2a839f6df (diff) | |
download | linux-1cb804b93f506dfba5fd684a8ea63706aaa8e709.tar.xz |
ARM: AM33XX: hwmod: Update and uncomment AES0 module data
Update the AES0 HIB2 module's hwmod data for the am33xx SoC.
Also, remove it from the '#if 0' block that its currently
inside so the data is actually available for use.
CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
[paul@pwsan.com: fixed lines causing sparse warnings]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_33xx_data.c')
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 51 |
1 files changed, 42 insertions, 9 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index a0e2925..556a122 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -417,7 +417,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = { * - clkdiv32k * - debugss * - ocp watch point - * - aes0 */ #if 0 /* @@ -498,25 +497,41 @@ static struct omap_hwmod am33xx_ocpwp_hwmod = { }, }, }; +#endif /* - * 'aes' class + * 'aes0' class */ -static struct omap_hwmod_class am33xx_aes_hwmod_class = { - .name = "aes", +static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = { + .rev_offs = 0x80, + .sysc_offs = 0x84, + .syss_offs = 0x88, + .sysc_flags = SYSS_HAS_RESET_STATUS, +}; + +static struct omap_hwmod_class am33xx_aes0_hwmod_class = { + .name = "aes0", + .sysc = &am33xx_aes0_sysc, }; static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = { - { .irq = 102 + OMAP_INTC_START, }, + { .irq = 103 + OMAP_INTC_START, }, { .irq = -1 }, }; +static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = { + { .name = "tx", .dma_req = 6, }, + { .name = "rx", .dma_req = 5, }, + { .dma_req = -1 } +}; + static struct omap_hwmod am33xx_aes0_hwmod = { - .name = "aes0", - .class = &am33xx_aes_hwmod_class, + .name = "aes", + .class = &am33xx_aes0_hwmod_class, .clkdm_name = "l3_clkdm", .mpu_irqs = am33xx_aes0_irqs, - .main_clk = "l3_gclk", + .sdma_reqs = am33xx_aes0_edma_reqs, + .main_clk = "aes0_fck", .prcm = { .omap4 = { .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET, @@ -524,7 +539,6 @@ static struct omap_hwmod am33xx_aes0_hwmod = { }, }, }; -#endif /* sha0 HIB2 (the 'P' (public) device) */ static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = { @@ -3464,6 +3478,24 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3 main -> AES0 HIB2 */ +static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = { + { + .pa_start = 0x53500000, + .pa_end = 0x53500000 + SZ_1M - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_aes0_hwmod, + .clk = "aes0_fck", + .addr = am33xx_aes0_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l4_fw__emif_fw, &am33xx_l3_main__emif, @@ -3545,6 +3577,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l4_hs__cpgmac0, &am33xx_cpgmac0__mdio, &am33xx_l3_main__sha0, + &am33xx_l3_main__aes0, NULL, }; |