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| author | Paul Walmsley <paul@pwsan.com> | 2013-01-26 07:58:17 (GMT) |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2013-01-29 21:59:58 (GMT) |
| commit | 562e54d13b6e0b17f72c9e629e1fd0b71e2a8a36 (patch) | |
| tree | 6cd99b816273da557611550722d3e0438d177553 /arch/arm/mach-omap2/powerdomain.h | |
| parent | 92493870196f52c743330db7b545b54b2abfda82 (diff) | |
| download | linux-562e54d13b6e0b17f72c9e629e1fd0b71e2a8a36.tar.xz | |
ARM: OMAP2+: powerdomain: fix whitespace, improve flag comments
Fix some whitespace problems introduced by commit
da03ce65b5431245b9cd20db3edaaa6b9f5c8dc1 ("OMAP3: powerdomain data:
add voltage domains"). Also, improve the documentation for the struct
powerdomain.flags field.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-omap2/powerdomain.h')
| -rw-r--r-- | arch/arm/mach-omap2/powerdomain.h | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index 909cc5c..140c360 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -43,18 +43,20 @@ #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON) -/* Powerdomain flags */ -#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ -#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits - * in MEM bank 1 position. This is - * true for OMAP3430 - */ -#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /* - * support to transition from a - * sleep state to a lower sleep - * state without waking up the - * powerdomain - */ +/* + * Powerdomain flags (struct powerdomain.flags) + * + * PWRDM_HAS_HDWR_SAR - powerdomain has hardware save-and-restore support + * + * PWRDM_HAS_MPU_QUIRK - MPU pwr domain has MEM bank 0 bits in MEM + * bank 1 position. This is true for OMAP3430 + * + * PWRDM_HAS_LOWPOWERSTATECHANGE - can transition from a sleep state + * to a lower sleep state without waking up the powerdomain + */ +#define PWRDM_HAS_HDWR_SAR BIT(0) +#define PWRDM_HAS_MPU_QUIRK BIT(1) +#define PWRDM_HAS_LOWPOWERSTATECHANGE BIT(2) /* * Number of memory banks that are power-controllable. On OMAP4430, the |