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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2010-08-02 10:18:18 (GMT)
committerTony Lindgren <tony@atomide.com>2010-08-02 10:18:18 (GMT)
commit3f9eaf0984952f69cb2d0c1b0f99b95b74742094 (patch)
tree40ea04df84bf010244f90fc538e5445063328d8a /arch/arm/mach-omap2
parent5643aebbc088332e6722750c45bcd83f61af071e (diff)
downloadlinux-3f9eaf0984952f69cb2d0c1b0f99b95b74742094.tar.xz
omap4: Add smc API to read AuxCoreBoot0 register
This patch adds a secure API to read AuxCoreBoot0 register to check the cpu boot status. It also moves the other smc APIs to common omap44xx-smc.S. This APIs should not be marked as __INIT because we need these to be present for CPU hotplug Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/omap-headsmp.S16
-rw-r--r--arch/arm/mach-omap2/omap44xx-smc.S25
2 files changed, 25 insertions, 16 deletions
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index ef0e7a0..6ae937a 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -47,19 +47,3 @@ hold: ldr r12,=0x103
b secondary_startup
END(omap_secondary_startup)
-
-ENTRY(omap_modify_auxcoreboot0)
- stmfd sp!, {r1-r12, lr}
- ldr r12, =0x104
- dsb
- smc #0
- ldmfd sp!, {r1-r12, pc}
-END(omap_modify_auxcoreboot0)
-
-ENTRY(omap_auxcoreboot_addr)
- stmfd sp!, {r2-r12, lr}
- ldr r12, =0x105
- dsb
- smc #0
- ldmfd sp!, {r2-r12, pc}
-END(omap_auxcoreboot_addr)
diff --git a/arch/arm/mach-omap2/omap44xx-smc.S b/arch/arm/mach-omap2/omap44xx-smc.S
index f61c777..1980dc3 100644
--- a/arch/arm/mach-omap2/omap44xx-smc.S
+++ b/arch/arm/mach-omap2/omap44xx-smc.S
@@ -30,3 +30,28 @@ ENTRY(omap_smc1)
smc #0
ldmfd sp!, {r2-r12, pc}
END(omap_smc1)
+
+ENTRY(omap_modify_auxcoreboot0)
+ stmfd sp!, {r1-r12, lr}
+ ldr r12, =0x104
+ dsb
+ smc #0
+ ldmfd sp!, {r1-r12, pc}
+END(omap_modify_auxcoreboot0)
+
+ENTRY(omap_auxcoreboot_addr)
+ stmfd sp!, {r2-r12, lr}
+ ldr r12, =0x105
+ dsb
+ smc #0
+ ldmfd sp!, {r2-r12, pc}
+END(omap_auxcoreboot_addr)
+
+ENTRY(omap_read_auxcoreboot0)
+ stmfd sp!, {r2-r12, lr}
+ ldr r12, =0x103
+ dsb
+ smc #0
+ mov r0, r0, lsr #9
+ ldmfd sp!, {r2-r12, pc}
+END(omap_read_auxcoreboot0)