diff options
| author | Len Brown <len.brown@intel.com> | 2011-01-12 23:06:06 (GMT) |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2011-01-12 23:06:06 (GMT) |
| commit | 56dbed129df3fdd4caf9018b6e7599ee258a5420 (patch) | |
| tree | b902491aef3a99efe0d9d49edd0f6e414dba654f /arch/arm/mach-pxa/smemc.c | |
| parent | 2a2d31c8dc6f1ebcf5eab1d93a0cb0fb4ed57c7c (diff) | |
| parent | f878133bf022717b880d0e0995b8f91436fd605c (diff) | |
| download | linux-56dbed129df3fdd4caf9018b6e7599ee258a5420.tar.xz | |
Merge branch 'linus' into idle-test
Diffstat (limited to 'arch/arm/mach-pxa/smemc.c')
| -rw-r--r-- | arch/arm/mach-pxa/smemc.c | 51 |
1 files changed, 17 insertions, 34 deletions
diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c index d6f6904..232b731 100644 --- a/arch/arm/mach-pxa/smemc.c +++ b/arch/arm/mach-pxa/smemc.c @@ -9,50 +9,37 @@ #include <linux/sysdev.h> #include <mach/hardware.h> - -#define SMEMC_PHYS_BASE (0x4A000000) -#define SMEMC_PHYS_SIZE (0x90) - -#define MSC0 (0x08) /* Static Memory Controller Register 0 */ -#define MSC1 (0x0C) /* Static Memory Controller Register 1 */ -#define SXCNFG (0x1C) /* Synchronous Static Memory Control Register */ -#define MEMCLKCFG (0x68) /* Clock Configuration */ -#define CSADRCFG0 (0x80) /* Address Configuration Register for CS0 */ -#define CSADRCFG1 (0x84) /* Address Configuration Register for CS1 */ -#define CSADRCFG2 (0x88) /* Address Configuration Register for CS2 */ -#define CSADRCFG3 (0x8C) /* Address Configuration Register for CS3 */ +#include <mach/smemc.h> #ifdef CONFIG_PM -static void __iomem *smemc_mmio_base; - static unsigned long msc[2]; static unsigned long sxcnfg, memclkcfg; static unsigned long csadrcfg[4]; static int pxa3xx_smemc_suspend(struct sys_device *dev, pm_message_t state) { - msc[0] = __raw_readl(smemc_mmio_base + MSC0); - msc[1] = __raw_readl(smemc_mmio_base + MSC1); - sxcnfg = __raw_readl(smemc_mmio_base + SXCNFG); - memclkcfg = __raw_readl(smemc_mmio_base + MEMCLKCFG); - csadrcfg[0] = __raw_readl(smemc_mmio_base + CSADRCFG0); - csadrcfg[1] = __raw_readl(smemc_mmio_base + CSADRCFG1); - csadrcfg[2] = __raw_readl(smemc_mmio_base + CSADRCFG2); - csadrcfg[3] = __raw_readl(smemc_mmio_base + CSADRCFG3); + msc[0] = __raw_readl(MSC0); + msc[1] = __raw_readl(MSC1); + sxcnfg = __raw_readl(SXCNFG); + memclkcfg = __raw_readl(MEMCLKCFG); + csadrcfg[0] = __raw_readl(CSADRCFG0); + csadrcfg[1] = __raw_readl(CSADRCFG1); + csadrcfg[2] = __raw_readl(CSADRCFG2); + csadrcfg[3] = __raw_readl(CSADRCFG3); return 0; } static int pxa3xx_smemc_resume(struct sys_device *dev) { - __raw_writel(msc[0], smemc_mmio_base + MSC0); - __raw_writel(msc[1], smemc_mmio_base + MSC1); - __raw_writel(sxcnfg, smemc_mmio_base + SXCNFG); - __raw_writel(memclkcfg, smemc_mmio_base + MEMCLKCFG); - __raw_writel(csadrcfg[0], smemc_mmio_base + CSADRCFG0); - __raw_writel(csadrcfg[1], smemc_mmio_base + CSADRCFG1); - __raw_writel(csadrcfg[2], smemc_mmio_base + CSADRCFG2); - __raw_writel(csadrcfg[3], smemc_mmio_base + CSADRCFG3); + __raw_writel(msc[0], MSC0); + __raw_writel(msc[1], MSC1); + __raw_writel(sxcnfg, SXCNFG); + __raw_writel(memclkcfg, MEMCLKCFG); + __raw_writel(csadrcfg[0], CSADRCFG0); + __raw_writel(csadrcfg[1], CSADRCFG1); + __raw_writel(csadrcfg[2], CSADRCFG2); + __raw_writel(csadrcfg[3], CSADRCFG3); return 0; } @@ -73,10 +60,6 @@ static int __init smemc_init(void) int ret = 0; if (cpu_is_pxa3xx()) { - smemc_mmio_base = ioremap(SMEMC_PHYS_BASE, SMEMC_PHYS_SIZE); - if (smemc_mmio_base == NULL) - return -ENODEV; - ret = sysdev_class_register(&smemc_sysclass); if (ret) return ret; |