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| author | Arnd Bergmann <arnd@arndb.de> | 2015-05-07 16:19:27 (GMT) |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2015-05-07 16:19:27 (GMT) |
| commit | d6bcc8069b27090f7e5bbe0521774f11c68a7001 (patch) | |
| tree | de8cc88628b8fb13fcb95fc4d2683317f16c0b43 /arch/arm/mach-rockchip/pm.h | |
| parent | 5ebe6afaf0057ac3eaeb98defd5456894b446d22 (diff) | |
| parent | 2a9fe3ca84afff6259820c4f62e579f41476becc (diff) | |
| download | linux-d6bcc8069b27090f7e5bbe0521774f11c68a7001.tar.xz | |
Merge tag 'v4.1-rockchip-socfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into fixes
Merge "ARM: rockchip: some soc-level fixes for 4.1" from Heiko Stübner:
Two fixes from Chris Zhong, fixing some suspend oddities.
And I've given up on the timer7 issue. While I initially thought
devices would either have both the grave mmu issue requiring a uboot
update and the timer7 issue or none, it looks like in all units in the
field the mmu issue got fixed while the timer7 issue stayed on.
So instead of making everybody wanting to use mainline jump through a
hoop just make sure timer7 is on on boot before we init the arch-timer.
* tag 'v4.1-rockchip-socfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
rockchip: make sure timer7 is enabled on rk3288 platforms
ARM: rockchip: fix undefined instruction of reset_ctrl_regs
ARM: rockchip: disable dapswjdp during suspend
Diffstat (limited to 'arch/arm/mach-rockchip/pm.h')
| -rw-r--r-- | arch/arm/mach-rockchip/pm.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h index 03ff31d..f8a747b 100644 --- a/arch/arm/mach-rockchip/pm.h +++ b/arch/arm/mach-rockchip/pm.h @@ -48,6 +48,10 @@ static inline void rockchip_suspend_init(void) #define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44 #define RK3288_PMU_PWRMODE_CON1 0x90 +#define RK3288_GRF_SOC_CON0 0x244 +#define GRF_FORCE_JTAG BIT(12) +#define GRF_FORCE_JTAG_WRITE BIT(28) + #define RK3288_SGRF_SOC_CON0 (0x0000) #define RK3288_SGRF_FAST_BOOT_ADDR (0x0120) #define SGRF_PCLK_WDT_GATE BIT(6) @@ -55,6 +59,10 @@ static inline void rockchip_suspend_init(void) #define SGRF_FAST_BOOT_EN BIT(8) #define SGRF_FAST_BOOT_EN_WRITE BIT(24) +#define RK3288_SGRF_CPU_CON0 (0x40) +#define SGRF_DAPDEVICEEN BIT(0) +#define SGRF_DAPDEVICEEN_WRITE BIT(16) + #define RK3288_CRU_MODE_CON 0x50 #define RK3288_CRU_SEL0_CON 0x60 #define RK3288_CRU_SEL1_CON 0x64 |