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authorMagnus Damm <damm@opensource.se>2012-01-10 08:44:39 (GMT)
committerPaul Mundt <lethal@linux-sh.org>2012-01-12 02:00:27 (GMT)
commitf40aaf6da14a4043d6361e0c7d74ada18e866059 (patch)
tree655a02f6a7a0ef50772c13c00fef992924bdeb78 /arch/arm/mach-shmobile/pm-r8a7779.c
parentf0a217a31a745421df98db0d14ebdadef11d734c (diff)
downloadlinux-f40aaf6da14a4043d6361e0c7d74ada18e866059.tar.xz
ARM: mach-shmobile: r8a7779 SMP support V3
This patch contains r8a7779 SMP support V3 - now including CPU hotplug offine and online support. The r8a7779 power domain code is tied together with SMP glue code which allows us to control the power domains via CPU hotplug. At this point the kernel boots with the 4 Cortex-A9 cores in SMP mode and all CPU cores except CPU0 can be hotplugged. The code in platsmp.c is quite far from pretty, but it is kept like that intentionally to avoid creating layers of code that will go away in the near future anyway. The code needs to be updated when some per-SoC handling code will be added to the ARM architecture, see the following patch for more information: "[RFC PATCH 0/3] Per SoC descriptor" Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/arm/mach-shmobile/pm-r8a7779.c')
-rw-r--r--arch/arm/mach-shmobile/pm-r8a7779.c30
1 files changed, 22 insertions, 8 deletions
diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c
index d9c56fe..c38ba7b 100644
--- a/arch/arm/mach-shmobile/pm-r8a7779.c
+++ b/arch/arm/mach-shmobile/pm-r8a7779.c
@@ -48,7 +48,9 @@ static void __iomem *r8a7779_sysc_base;
#define SYSCISR_RETRIES 1000
#define SYSCISR_DELAY_US 1
-#ifdef CONFIG_PM
+#if defined(CONFIG_PM) || defined(CONFIG_SMP)
+
+static DEFINE_SPINLOCK(r8a7779_sysc_lock); /* SMP CPUs + I/O devices */
static int r8a7779_sysc_pwr_on_off(struct r8a7779_pm_ch *r8a7779_ch,
int sr_bit, int reg_offs)
@@ -86,9 +88,12 @@ static int r8a7779_sysc_update(struct r8a7779_pm_ch *r8a7779_ch,
unsigned int isr_mask = 1 << r8a7779_ch->isr_bit;
unsigned int chan_mask = 1 << r8a7779_ch->chan_bit;
unsigned int status;
+ unsigned long flags;
int ret = 0;
int k;
+ spin_lock_irqsave(&r8a7779_sysc_lock, flags);
+
iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
do {
@@ -112,6 +117,8 @@ static int r8a7779_sysc_update(struct r8a7779_pm_ch *r8a7779_ch,
iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
out:
+ spin_unlock_irqrestore(&r8a7779_sysc_lock, flags);
+
pr_debug("r8a7779 power domain %d: %02x %02x %02x %02x %02x -> %d\n",
r8a7779_ch->isr_bit, ioread32(r8a7779_sysc_base + PWRSR0),
ioread32(r8a7779_sysc_base + PWRSR1),
@@ -121,12 +128,12 @@ static int r8a7779_sysc_update(struct r8a7779_pm_ch *r8a7779_ch,
return ret;
}
-static int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch)
+int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch)
{
return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_off);
}
-static int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch)
+int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch)
{
return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_on);
}
@@ -142,6 +149,14 @@ static void __init r8a7779_sysc_init(void)
iowrite32(0, r8a7779_sysc_base + SYSCIMR);
}
+#else /* CONFIG_PM || CONFIG_SMP */
+
+static inline void r8a7779_sysc_init(void) {}
+
+#endif /* CONFIG_PM || CONFIG_SMP */
+
+#ifdef CONFIG_PM
+
static int pd_power_down(struct generic_pm_domain *genpd)
{
return r8a7779_sysc_power_down(to_r8a7779_ch(genpd));
@@ -223,13 +238,12 @@ struct r8a7779_pm_domain r8a7779_impx3 = {
}
};
-#else /* CONFIG_PM */
-
-static inline void r8a7779_sysc_init(void) {}
-
#endif /* CONFIG_PM */
void __init r8a7779_pm_init(void)
{
- r8a7779_sysc_init();
+ static int once;
+
+ if (!once++)
+ r8a7779_sysc_init();
}