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| author | Thor Thayer <tthayer@opensource.altera.com> | 2016-03-21 16:01:43 (GMT) |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2016-03-29 08:30:07 (GMT) |
| commit | 8b39ab7290d571b91867b15c02a59edf0a5b00bb (patch) | |
| tree | d6c994fd7a08555a89bfb641eb348b6513489025 /arch/arm/mach-socfpga/l2_cache.c | |
| parent | 811fce4f2a7aea0cd93815d0eaf42fbcc98bd930 (diff) | |
| download | linux-8b39ab7290d571b91867b15c02a59edf0a5b00bb.tar.xz | |
Documentation, dt, socfpga: Add Altera Arria10 L2 cache binding
Add the device tree bindings needed to support the Altera L2 cache on
the Arria10 chip. Since all the peripherals share IRQs, the IRQ fields
are now in the ecc_manager.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1458576106-24505-7-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'arch/arm/mach-socfpga/l2_cache.c')
0 files changed, 0 insertions, 0 deletions